HDL_Lab1 - EECC 0306- 351: Hardware Description Language...

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EECC 0306- 351: Hardware Description Language Lab LAB#1 The objectives of this lab exercise are: 1) To learn how to write a simple VHDL source code and compile it using the ModelSim’s tools. 2) To write and simulate (test) different models of a simple combinational logic. 3) To learn how to define waveforms in VHDL using signal assignment statement. 1) Write the entity description for the 74x181 (data sheet included). Use bit and bit_vector types. Make the description well commented. To check the syntax simply compile your source code. 2) Write a VHDL model (entity and architecture) of a combinational logic circuit given. a) Describe it using just one line in your architecture body (one boolean equation). b) Add the second architecture, which is to describe the same logic using 3 equations (3 signal assignment statements). You have to add a few internal signals to do this. c) Add the third architecture, which is to model 10 ns propagation delays of all the gates - use “ after ” clause. Simulate all architectures to prove the correctness of your models.
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This note was uploaded on 05/06/2010 for the course EECC 0306-351 taught by Professor Marcinlukowiak during the Winter '10 term at RIT.

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HDL_Lab1 - EECC 0306- 351: Hardware Description Language...

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