HDL_Lab2 - simple signal assignment statement and after...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
EECC 0306- 351: Hardware Description Language Lab LAB#2 The objectives of this lab exercise are: 1) To learn how to use structural, data flow and behavioral description of a design entity. 2) To understand simulation process of concurrent statements and delta delays. 1) Write and simulate the description of the 74LS153 circuit (2 separate four-to-one Multiplexers – datasheet attached) a) Using Selected Signal Assignment (SSA) statement ( architecture DF - data flow) – use one S SA for one multiplexer! (description without any delays) . b) Using processes and case statements ( architecture BEHV behavioral ) - one process for each multiplexer! (description which includes total (the worst case- 14 ns) delay from inputs to outputs). c) Using inverters and 3 input “AND” and “OR” gates ( architecture STRUCT - structural ). Step 1: and4, or4 ) and for an inverter ( inv ). “and” and “or” gate introduce 10 ns delay and inverter 5 ns. To describe the gates, use
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: simple signal assignment statement and after clause . Step 2: Using these gates describe one Multiplexer - intermediate design (structurally). Later on you will use the multiplexer as a component to describe the final 74LS153 circuit, which is composed of two such multiplexers. In part b) and c) use constants for the description of delays. sig <= after const_value; not sig <= after 14 ns; Implementation details for the entity of 74LS153 circuit inputs: outputs: G1, G2, A,B single bit - std_logic C1, C2 4-bit - std_logic_vector Y1, Y2 1 bit std_logic 2) Explain the meaning of Delta delays and concurrent statement on the basic of attached VHDL code and list (Lab2Appendix.pdf) . Draw appropriate waveforms show how changes on signals trigger the execution of another statements make delta cycles visible. Draw the schematic of corresponding circuit. Report: Follow the report format requirements in mycourses website....
View Full Document

Ask a homework question - tutors are online