Unformatted text preview: simple signal assignment statement and after clause . Step 2: Using these gates describe one Multiplexer - intermediate design (structurally). Later on you will use the multiplexer as a component to describe the final 74LS153 circuit, which is composed of two such multiplexers. In part b) and c) use constants for the description of delays. sig <= …………… after const_value; not sig <= …………… after 14 ns; Implementation details for the entity of 74LS153 circuit inputs: outputs: G1, G2, A,B single bit - std_logic C1, C2 – 4-bit - std_logic_vector Y1, Y2 1 bit – std_logic 2) Explain the meaning of Delta delays and concurrent statement on the basic of attached VHDL code and list (Lab2Appendix.pdf) . Draw appropriate waveforms – show how changes on signals trigger the execution of another statements – make delta cycles visible. Draw the schematic of corresponding circuit. Report: Follow the report format requirements in mycourses website....
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This note was uploaded on 05/06/2010 for the course EECC 0306-351 taught by Professor Marcinlukowiak during the Winter '10 term at RIT.
- Winter '10