HDL_lab3 - EECC 0306- 351: Hardware Description Language...

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EECC 0306- 351: Hardware Description Language Lab -1- LAB#3 1) The objective of this lab is to go through the design process of a simple combinational circuit and its testbench. 1) Design a two-out-of-five code detector. The device receives as inputs 5 separate bits. The detector output is logic ’1’ for any code word that has exactly two 1’s on its inputs and is logic ’0’ otherwise. Implementation details for the entity of two-out-of-five circuit inputs: outputs: a, b, c, d, e 1 bit - std_logic y 1 bit – std_logic a) Develop an algorithmic “behavioral” architecture for the detector (use concatenation operator & – to group input signals into one object (variable or signal) - and a loop statement ). No delays for this model. b) Design hardware to implement this logic (MUX with 3 select lines and some additional gates). Draw the schematic with labels for all inputs, outputs and internal connections. Use the same names for your architecture. Describe MUX using process module
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HDL_lab3 - EECC 0306- 351: Hardware Description Language...

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