HDL_Lab4 - EECC 0306- 351: Hardware Description Language...

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EECC 0306- 351: Hardware Description Language Lab -1- LAB#4 The objectives of this lab exercise are: 1) To go through the design process of a synchronous circuit – 4-bit serial adder. 2) To test the model of a serial adder using a full test bench. 1) a) Develop a VHDL entity declaration for the serial adder (all ports have to be std_logic and std_logic_vector types). Implementation details for a 4-bit serial adder entity inputs: outputs: in_a 4 bits in_b 4 bits control 2 bits (s1, s0) clk 1 bit (100ns period) reset_al 1 bit (asynchronous active low) Sum 4 bits carry 1 bit b) Implement the serial adder in a structural way only. Your description is to be composed of 5 components and a few internal signals (internal descriptions of all components are to be based on processes): component describing 1 bit full_adder ( introduces 8 ns delay ) , component describing d - flip flop with enable and asynchronous reset ( introduces 2 ns delay ) , component describing 2 inputs and gate (
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This note was uploaded on 05/06/2010 for the course EECC 0306-351 taught by Professor Marcinlukowiak during the Winter '10 term at RIT.

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HDL_Lab4 - EECC 0306- 351: Hardware Description Language...

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