HDL_Lab5 - EECC 0306- 351: Hardware Description Language...

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EECC 0306- 351: Hardware Description Language Lab LAB#5 The objectives of this lab exercise are: 1) To go through the design process of a behavioral and structural description of a control block (State Machine) for the serial adder. 2) To test the serial adder with the control block. 1) The state machine given below can be used as a control block for the serial adder designed in the previous lab. It is a Moore’s machine since outputs depend only on the current state. Implementation details for a Control Block entity inputs: outputs: (ready, reset_SA, s1, s0) start 1 bit clk 1 bit reset_SM 1 bit (asynchronous active high) control 4 bits
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EECC 0306- 351: Hardware Description Language Lab a) Write a behavioral VHDL description of the state machine (2 or 3 processes). Use enumerated type to define the states (use the same names as in the diagram). Make your machine sensitive to the rising edge of a clock signal! b)
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This note was uploaded on 05/06/2010 for the course EECC 0306-351 taught by Professor Marcinlukowiak during the Winter '10 term at RIT.

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HDL_Lab5 - EECC 0306- 351: Hardware Description Language...

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