HDL_Lab6 - EECC 0306 351 Hardware Description Language Lab...

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EECC 0306- 351: Hardware Description Language Lab 1 LAB # 6 The objectives of this lab exercise are: 1) To go through the design process of a Combinational Multiplier for unsigned binary numbers - practice using generate statement and generics. 2) To test the Combinational Binary Multiplier using testbench and files . 3) To synthesize the description of the general nxn multiplier. To practice synthesis for various target technologies and various values of the generic n . 1) Design and simulate the structural architecture of the generic, n x n bits Combinational Binary Multiplier that consists of AND gates, Half- and Full-Adders. Since the multiplier has a regular structure, we can use generate ” statements to instantiate components (AND gates and Adders). Use generic to set the number of bits - n . The general idea of such a multiplier is that multiplication can be considered as a series of repeated additions in the way as it is presented for 4x4 bits multiplier in Fig. 1 . Each step of the addition generates
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This note was uploaded on 05/06/2010 for the course EECC 0306-351 taught by Professor Marcinlukowiak during the Winter '10 term at RIT.

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HDL_Lab6 - EECC 0306 351 Hardware Description Language Lab...

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