HDL_lab7 - EECC 0306- 351: Hardware Description Language...

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EECC 0306- 351: Hardware Description Language Lab LAB#7 This lab is for teams of 2 students. The objective of this lab exercise is: 1. To practice behavioral description in VHDL (using 2D arrays, reading and writing from/to files) by implementation of two basic image processing algorithms - contrast stretching, and median filtering. 2. To synthesize the behavioral description of the state machine from lab#5. Practice synthesis for various coding styles of states. 3. Use Verilog HDL to construct and simulate models of 74LS153 and 74LS139. Test them using Veri- log’s test bench with initial statement. 1) Design and simulate (run for any time – e.g. 1 ns) behavioral architectures for the following image processing algorithms: contrast stretching (to enhance the contrast of an image) and median filtering (to reject salt and pepper noise and smoothing). Each of the architectures is to be described with the use of 3 separate processes. The first process reads in an im- age from a textual file, the second one performs an operation on the image and the third one writes the result to the textual output file. To model memories (for storing images) declare appropriate signals in your architecture (2D arrays of integers from 0 to 255). You will need 2 such objects (signals or shared variables) – one for the original image and the second one for the results. You will need 1D array of integers to calculate the histogram of an image (to model the contrast stretching algorithm). Use internal signals to enable the communication among processes !
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This note was uploaded on 05/06/2010 for the course EECC 0306-351 taught by Professor Marcinlukowiak during the Winter '10 term at RIT.

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HDL_lab7 - EECC 0306- 351: Hardware Description Language...

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