Week01_2 - Types Every data object in VHDL can hold a value...

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Types Every data object in VHDL can hold a value that belongs to a set of values. This set of values is specified by using a type declaration. All the possible types that can exist in the VHDL language can be categorized into the fallowing categories: 1. Scalar types: values belonging to these types appear in sequential order. 2. Composite types: these are composed of elements of a single type (an array type) or elements of different types (record type). 3. Access types: these provide access to objects of a given type (via pointers). 4. File types: these provide access to objects that contain a sequence of values of a given type. VHDL is a strongly typed language – you cannot assign an object of one type to the object of another type. Types Types Scalar Enumerated Integer Real Physical Composite File Access Array Record
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Types Physical Type - TIME (data type which is composed of a numerical value and a physical unit) type voltage is range –1.0E18 to 1.0E18 units nV; -- nanovolt uV = 1000 nV; -- mikrovolt mV = 1000 uV; -- milivolt V = 1000 mV; -- volt kV = 1000 V; -- kilovolt end units voltage ; You may declare your own physical types it is used to delay the execution of statements for a certain amount of time, to create waveforms or to model gate and propagation delays. Signals of data type 'time' can be multiplied or divided by 'integer' and 'real' values. The result of these operations remains of data type 'time'. The internal resolution of VHDL simulators is set to fs. Types type word is array ( 0 to 31 ) of bit; SIGNAL a: BIT_VECTOR (0 TO 3); -- ascending range SIGNAL b: BIT_VECTOR (3 DOWNTO 0); -- descending range a <= "0111"; -- double quotes used for vectors b <= "0101"; This means that: a(0) = '0' b(0) = '1' a(1) = '1' b(1) = '0' a(2) = '1' b(2) = '1' a(3) = '1' b(3) = '0' Array Type The array type allows declaring composite objects whose elements can be of the same type. type array_type_name is array (discreet range ) of element_type;
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Types type t_a is array (0 to 7, 15 downto 0) of bit ; signal s_a : t_a; Alternate description of a 2D Array type t_a is array (0 to 7) of bit_vector ( 15 downto 0 ) ; Record Type The record type allows declaring composite objects whose elements can be of different types. type record_type_name is record element_name : element type; {element_name : element type;} end record record_type_name; This is the main difference from arrays, which must have all elements of the same type. All elements are declared with individual names together with subtype indication. If two or more elements are of the same subtype they can be declared together. The names of elements in each record must be distinct. The same element name,
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This note was uploaded on 05/06/2010 for the course EECC 0306-351 taught by Professor Marcinlukowiak during the Winter '10 term at RIT.

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Week01_2 - Types Every data object in VHDL can hold a value...

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