Week02_1 - -- delta cycles - simple example entity...

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Unformatted text preview: -- delta cycles - simple example entity concurrently is port ( a, b, c : in bit; y : out bit ); end concurrently; architecture df_concurrently of concurrently is signal s1, s2 : bit ; begin s1 <= a and b; y <= s1 or s2; s2 <= not c; end df_concurrently;-- delta cycles - simple example entity concurrently is port ( a, b, c : in bit; y : out bit ); end concurrently; architecture df_concurrently of concurrently is signal s1, s2 : bit ; begin s1 <= a and b; y <= s1 or s2; s2 <= not c; end df_concurrently; ns +delta a b c y s1 s2 0 +0 0 0 1 0 0 0 10 +0 0 0 0 0 0 10 +1 0 0 0 0 0 1 10 +2 0 0 0 1 0 1 20 +0 0 1 1 1 0 1 20 +1 0 1 1 1 0 20 +2 0 1 1 0 0 ns +delta a b c y s1 s2 0 +0 0 0 1 0 0 0 10 +0 0 0 0 0 0 10 +1 0 0 0 0 0 1 10 +2 0 0 0 1 0 1 20 +0 0 1 1 1 0 1 20 +1 0 1 1 1 0 20 +2 0 1 1 0 0 initialization (a, b =0, c=1) VHDL versus other programming languages: A fundamental difference between VHDL programs and conventional programming languages is that c oncurrency is a natural part of the systems described in VHDL The execution of the statements is determined by the flow of signal values , rather than textual order. A fundamental difference between VHDL programs and conventional programming languages is that c oncurrency is a natural part of the systems described in VHDL The execution of the statements is determined by the flow of signal values , rather than textual order. Simulation Flow behavior of a discrete event simulator. Execute the simulation models of all components affected by new signal values Initialize model; t = 0 Advance to next event More events? Yes Delta delay? Advance time Update signals Execute model Project new signal values End of simulation Yes repeat until event list is empty, or present simulation time has expired Simulation cycle Advance simulation time to that of the event with the smallest time stamp in the event list. This is the event at the head of the list. The delta cycles are orthogonal to the simulation time. So at a fixed simulation time several delta cycles can be executed. The delta cycles are orthogonal to the simulation time. So at a fixed simulation time several delta cycles can be executed. Simulation Flow Simulation Flow There are several kinds of design libraries: work library; where the designer puts "by default" the compiled descriptions IEEE library; where the designer finds standard logic system and the corresponding types and functions user defined libraries; where the designer puts specific types of compiled components ( library AMS_gates ; ) The source code analysis involves the lexical and the syntactical analysis. If both the lexis and the syntax are correct the compiler generates an intermediary code stored in the design library ....
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Week02_1 - -- delta cycles - simple example entity...

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