Week05_StateMachines_1

Week05_StateMachines_1 - Modeling State Machines in VHDL...

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Modeling State Machines in VHDL State machines are sequential circuits that are constructed using combinational logic and a number of memory elements with some or all of the memory outputs fed back into combinational logic forming a feedback path (loop). There are several versions of state machines. The standard versions known in theory are Moore and Mealy machines. For several reasons it is for example recommended to place additional storing elements (registers, Flip Flops) at the module outputs. By doing this, additional versions of finite state machines can be build. Generally every finite state machine can be described in VHDL either by one two or three separated processes. The description with one process can be used only for simulation purposes. Guidelines and advantages or drawbacks of the different variants will be given. Moore state machine A finite state machine in which the outputs change only due to a change of a state (to calculate the outputs combinational logic is used) The output vector (Y) is a function of the state vector (S)
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This note was uploaded on 05/06/2010 for the course EECC 0306-351 taught by Professor Marcinlukowiak during the Winter '10 term at RIT.

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Week05_StateMachines_1 - Modeling State Machines in VHDL...

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