Week06_1 - generics and constants VHDL provides two ways of...

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VHDL provides two ways of parameterizing a design or a module, that means the behavior description depends on some parameters. One way to parameterize a design is to use constants and the second one is to use generics. Constant C identical in all referencing units Generic G can be different within each entity. The intention is that by changing the parameter the behavior will change accordingly. generics and constants package my_package is constant CMaxValue :integer := 15; end my_package; entity ccounter is port (... count : out integer range 0 to CMaxValue ); end ccounter; architecture beh of ccounter is signal scount: integer range 0 to CMAXValue ; begin process (clk) begin if clk'event and clk='1' then if scount < CMaxValue then scount <= scount + 1; else scount <= 0 ; end if; end if; end process; count <= scount; end beh; Constants are fixed for the complete design. Instantiations of ccounter produce exactly the same counter.
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entity gcounter is generic (MAX_VALUE : integer := 15); port (... count : out integer range 0 to CMaxValue ); end gcounter; architecture beh of gcounter is signal scount: integer range 0 to CMAXValue ; begin process (clk) begin if clk'event and clk='1' then if scount < CMaxValue then scount <= scount + 1; else scount <= 0 ; end if; end if; end process; count <= scount; end beh; If you want to instantiate counters with different counter ranges in one design you will have to switch to generics. Generics are defined like the ports in the entity definition and receive their values during the step of component instantiation. Therefore, in addition to the port map, a generic map is required to provide these values. Generics may be given a default value in the generic clause which will be used if the generic is not explicitly assigned a value. Simplified Syntax: generic ( generic_interface_list ); entity two_counters is port (...); end entity; architecture Structural of two_counters is component gcounter generic (MAX_VALUE: integer := 15); port (...); end component; begin COUNTER1 : gcounter port map (...); -- MAX_VALUE with default value COUNTER2 : gcounter generic map (MAX_VALUE => 31) port map (...); ... end
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This note was uploaded on 05/06/2010 for the course EECC 0306-351 taught by Professor Marcinlukowiak during the Winter '10 term at RIT.

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Week06_1 - generics and constants VHDL provides two ways of...

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