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Week07_2 - library ieee use ieee.std_logic_1164.all use...

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library ieee; use ieee.std_logic_1164. all ; use ieee.std_logic_TEXTIO. all ; use STD.TEXTIO. all; -- reading test vectors from file entity fulladder_tb is end fulladder_tb; architecture fulladder_tb of fulladder_tb is component adder -- Component declaration of the unit under test port ( A, B, CIN : in std_logic; SUM, COUT : out std_logic); signal A, B, CIN : std_logic; -- Stimulus signals - signals mapped to the -- input and inout ports of tested entity signal SUM, COUT : std_logic; -- Observed signals - signals mapped to -- the output ports of tested entity file INFILE : TEXT open READ_MODE is "input.txt"; -- 0 0 0 -- format of the input file: -- 0 0 1 -- the columns from left to right are values of A, B, CIN -- 0 1 0 -- 0 1 1 -- 1 0 0 -- 1 0 1 -- 1 1 0 -- 1 1 1 begin UUT : adder port map (A => A, B => B, CIN => CIN, SUM => SUM, COUT => COUT ); STIM: process variable vLine : line; -- pointer to string variable vA,vB,vCIN : std_logic; begin while not ( endfile(fINFILE)) loop -- while not end of file readline(fINFILE, vLine); -- read line of a file read(vLine,vA); -- each READ procedure extracts data read(vLine,vB); -- from the beginning of the string read(vLine,vCIN); -- value designed by parameter vLine A <= vA; B <= vB; CIN <= vCIN; wait for
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