The behavioral description uses HDL code to model the design at system-level. The register transfer level completely models your design in detail. All clocks are defined and all registers declared.ASIC or FPGABasic Design MethodologySynthesis tools are used hereSynthesis Synthesis process converts user's hardware model from textual file into structural circuit description. Here, we use VHDL as textual file, thus this process is called VHDL synthesis. Synthesizable VHDL uses very small subset of whole VHDL grammar. Most descriptions are consisted of simple statements. Use simple statements as possible. Here are some examples of unsynthesizable statements: Unconstrained loop, file, assert, after, and so on. There are two levels of digital circuits synthesis: •high level synthesis where the algorithms are mapped onto register transferarchitectures •register transfer synthesis where RTL model is mapped into thefunctionally corresponding gate level structure
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