Week08_1Verilog

Week08_1Verilog - Introduction to Verilog HDL First...

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Introduction to Verilog HDL First developed by Gateway Design Automation – 1983 OVI: Open Verilog International, 1990 IEEE standard, 1995 (IEEE Std 1364-1995) Design description Styles - RTL (dataflow) description - Behavioral description - Structural (gate level) description - any mix of above Syntax based on and C (e.g. comments are exactly like in C, case sensitive) Closer to hardware then VHDL (types, objects, operators) Module Introduction to Verilog HDL module (port1, port2, port3, port4); input port1, port2; output [1:0] port3; inout port4; // statements endmodule - basic structure (building block) in Verilog (like entity-architecture pair in VHDL) - defines a device or part of a device when description is hierarchical (modules can call another modules) - one module may have only one ”architecture” module module_name (port_list); declarations: input, output, inout, reg, wire, parameter, function, task, . .. statements: initial statement, always statement, module instantiation, continuous statement, . .. endmodule template of module port modes in Verilog are like in VHDL (input, output or inout), size of the port is declared together with mode declaration
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Introduction to Verilog HDL - Data types and objects Nets (wires) model physical connections; they don’t hold their value – they must be driven by a driver. nets
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This note was uploaded on 05/06/2010 for the course EECC 0306-351 taught by Professor Marcinlukowiak during the Winter '10 term at RIT.

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Week08_1Verilog - Introduction to Verilog HDL First...

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