Specifying values, parameters8’b01110011 // 8-bit binary number12’hA2D// 1010 0010 1101 in binary12’hCx5// 1100 xxxx 0101 in binary25// signed decimal number, 32 bits1’b0// logic 01’b1// logic 1Verilog allows specification of numbers in decimal, hexadecimal, octal and binary formats. Whenever a number is supposed to be written in a non-decimal format, it has be preceded by a single quote and a letter denoting the base.<size>’<base><number>an ‘integer’ is treated as a 2’s complement signed integer (default representation-32 bit). When ‘integer’ is used, the synthesis system often carries out a data flow analysis of the model to determine its actual size.Constant in Verilog are called parameters.parameterBusWidth = 8;//reg[BusWidth-1:0] DataBus;parameterup = 2’b00, down = 2’b01;parameterPDelay = 3;//assign #Pdelay y=x;module MUX (data, select, out);input [7:0] data;input [2:0] select;output out;assign out = data [select];endmodulemodule deMUX (out, in, select);input in;input [1:0] select;output [3:0] out;assign out [select] = in;endmodule
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