Week08_2Verilog

Week08_2Verilog - Specifying values, parameters Verilog...

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Specifying values, parameters 8’b01110011 // 8-bit binary number 12’hA2D // 1010 0010 1101 in binary 12’hCx5 // 1100 xxxx 0101 in binary 25 // signed decimal number, 32 bits 1’b0 // logic 0 1’b1 // logic 1 Verilog allows specification of numbers in decimal, hexadecimal, octal and binary formats. Whenever a number is supposed to be written in a non-decimal format, it has be preceded by a single quote and a letter denoting the base. <size>’<base><number> an ‘integer’ is treated as a 2’s complement signed integer (default representation- 32 bit). When ‘integer’ is used, the synthesis system often carries out a data flow analysis of the model to determine its actual size. Constant in Verilog are called parameters. parameter BusWidth = 8; // reg [BusWidth-1:0] DataBus; parameter up = 2’b00, down = 2’b01; parameter PDelay = 3; // assign # Pdelay y=x; module MUX (data, select, out); input [7:0] data; input [2:0] select; output out; assign out = data [select]; endmodule module deMUX (out, in, select); input in; input [1:0] select; output [3:0] out; assign out [select] = in; endmodule
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Operators Arithmetic operators *, /, +, -, % Logical operators ! (logical negation), && (logical AND), | | (logical OR) Bitwise operators ~, &, |, ^, ~^ Relational operators >, <, >=, <=, ==, != Shift operators >>, << Reduction operators &, ~&, |, ~|, ^, ~^ Concatenation { } Replication { { } } Conditional <condition> ? <expression1> : <expression2> The presence of a ‘z’ or ‘x’ in a reg or wire being used in an arithmetic expression results in the whole expression being unknown (‘x’).
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This note was uploaded on 05/06/2010 for the course EECC 0306-351 taught by Professor Marcinlukowiak during the Winter '10 term at RIT.

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Week08_2Verilog - Specifying values, parameters Verilog...

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