Week09_1Testbench

Week09_1Testbench - assert false report "all...

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Register clke clk addr data_in rst_n data_out n n wr_n m Register 2 m words of n bits UUT - m=2, n=4 stimulus_verification clk Testbench clke clk addr data_in rst_n data_out n n wr_n m clock generator clk File transactions.txt RESET 5 WRITE 00 0001 WRITE 01 0010 WRITE 10 0100 WRITE 11 1000 WAIT_ 6 READ_ 11 1000 READ_ 10 0100 READ_ 01 0010 READ_ 00 0001 data_out RESET # clocks reset is low WAIT_ # clocks clk enable is low WRITE addr data_in READ_ addr expected data_out Testbench for register
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verification: process file fdata_in : text open read_mode is "register.txt"; variable ll : line; variable vcommand : string (1 to 5); variable vctw : integer; variable vaddr : std_logic_vector (1 downto 0); variable vd_in : std_logic_vector (3 downto 0); variable vd_out : std_logic_vector (3 downto 0); constant cpropagation : time := 10 ns; begin while not endfile(fdata_in) loop readline(fdata_in,ll); read(ll,vcommand); case vcommand is end case; end loop; ---------------------------------- wait until rising_edge(clk);
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Unformatted text preview: assert false report "all test done: "&time'image(now) severity failure; end process; when "RESET" => read(ll,vctw); rst_n <= '0'; for i in 1 to vctw loop wait until rising_edge(clk); end loop; rst_n <= '1'; report "reset done"; when "WRITE" => read(ll,vaddr); read(ll,vd_in); rst_n <= '1'; en <= '1'; wr_n <= '1'; addr <= vaddr; d_in <= vd_in; wait until rising_edge(clk); report "write done"; when "WAIT_" => read(ll,vctw); en <= 0' for i in 1 to vctw loop wait until rising_edge(clk); end loop; en <= '1' when "READ_" => read(ll,vaddr); read(ll,vd_out); rst_n <= '1'; en <= '1'; wr_n <= '0'; addr <= vaddr; wait until rising_edge(clk); wait for cpropagation; assert d_out = vd_out report "wrong value output severity note; report "read&test done"; when others => report "wrong command: "&vcommand; Testbench for register...
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Week09_1Testbench - assert false report "all...

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