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THE UNIVERSITY OF TEXAS at DALLASDEPARTMENT OF ELECTRICALAND COMPUTER ENGINEERINGCE/EEDG 6301 Assignment # 2 Spring 2020Hardware Language Homework1. Write a generalized testbench function which enumerates all of the possible combinatorial
input states for a given number of input pins.The number of input pins is to be aparameter or generic.a) Write the function in Verilogb) Write the function in VHDL2. Design an 8 bit counter in both of the Verilog and VHDL languages and simulate andtest in the Synopsys environment.You should create a behavior and test it with theappropriate test bench. Attached is a tutorial on how to use Synopsys.3. Design a negative edge triggered (activated on the falling edge of the clock) D-type flip-flop with asynchroous preset in behavioral language in both Verilog and VHDL. Connectthe flip-flow so to create a divide by two counter. Build a test bench and test the circuitin both Verilog and VHDL. Use the Xilinx tools on engnx to simulate. Use the ISIMsimulator to verify your design.