ahdl_bis - Department of Electrical and Computer...

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Department of Electrical and Computer Engineering Slide 1 Robert Betz: 97 Hardware Description Languages (HDLs) Introduction Two main hardware description languages will be treated in this course: Altera Hardware Description Language (AHDL), and Very High Speed Integrated Circuit Hardware Description Language (VHDL). VHDL is an IEEE Standard (IEEE Std 1076-1987 or 1076-1993). Altera Hardware Description Language (AHDL) Introduction Limitations: These notes are not attempting to describe the full details of AHDL, but just to give the flavour of the language and point out some of its features. In most cases further detail can be obtained from the MAX+PLUS II on-line help system. Reference: “MAX+PLUS II Text Editor and AHDL Manual”, Altera. High level modular language that is completely integrated into the MAX+PLUS II development system. Main features of AHDL: (i) State machine, truth tables, boolean equations, and group opera- tions are supported and implemented in a user friendly format. (ii)Text, graphic and waveform files can be intermixed in a design hierarchy. (iii)Frequently used constants and prototypes. including prototypes of standard TTL, bus, and EPLD optimized Macrofunctions can be stored in Include Files ( .inc ) and incorporated into any Text Design File ( .tdf ).
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Department of Electrical and Computer Engineering Slide 2 Robert Betz: 97 (iv)Device resources can be user specified or assigned automati- cally. Text Design File Sections (i) Title Statement (Optional) – provides comments for the Report Files ( .rpt ) generated by the system. (ii) Constant Statement (Optional) – specifies a symbolic name that can be substituted for a constant. (iii) Function Prototype Statement – declares the ports of a macro- function or primitive and the order in which those ports must be declared in an in-line reference. (iv) Include Statement (Optional) – specifies an Include File ( .inc ) that replaces the Include statement in the TDF. (v) Options Statement (Optional) – sets the Turbo and Security Bits of Altera devices and determines how product terms are allo- cated. (vi) Design Sections (Required/Optional) – specifies device, clique, chip, pin, and macrocell assignments, and logic options. (vii) Subdesign Section (Required) – declares the input, output, and bidirectional ports of a design. (viii) Variable Section (Optional) – declares variables that represent and hold internal information. (ix) Logic Section (Required) – defines the logical operations of the design. AHDL is a concurrent language – i.e. all behaviour described in the logic section is evaluated at the same time and not sequentially as in a conventional programming language. To include lower level design files in a higher level TDF a function prototype statement must be included.
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Department of Electrical and Computer Engineering Slide 3 Robert Betz: 97 Title Statement Constant Statement Function Prototype Statement Include Statement Options Statement Design Section Subdesign Section Variable Section Logic Section Constant Function Prototype Include Files (.INC) con-
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This note was uploaded on 05/07/2010 for the course DMO electro23 taught by Professor Taflove during the Spring '10 term at Unicamp.

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ahdl_bis - Department of Electrical and Computer...

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