Lec13 - System Specifications and Modeling Lecture 13 Last...

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Unformatted text preview: System Specifications and Modeling Lecture 13 Last Lecture Test Paper I discussion Architecture Taxonomy FSM Data Path Model FSMD CISC Today's Lecture Architecture Taxonomy Pipelining RISC VLIW SIMD/MIMD Pipelining Is an implementation technique whereby multiple instructions are overlapped in execution. Because the processor works on different steps of the instruction at the same time, more instructions can be executed in a shorter period of time. Example Let's say that there are four loads of dirty laundry that need to be washed, dried, and folded. washer takes 30 minutes, Dryer takes 40 minutes 20 minutes to fold the clothes ONE WAY Not very efficient!!! The other smarter way RISC (Reduced Instruction Set Computer) Optimized to achieve: short clock cycles small numbers of cycles per instruction efficient pipelining of instruction streams Consists of: a large register file an ALU Load/store architecture the data is brought to the register file by load instructions ALU operates on data the data is returned to the memory by store instructions The register file contains all the operands and the results for program computation The larger the register file is, the smaller the number of load and store instructions in the code RISC Architecture RISC operation: An instruction is fetched into the Instruction register The instruction is then decoded and the appropriate operands are fetched from the register file The ALU performs the required operation or data is transformed from/to data cache Repetition RISC pipeline A RISC processor pipeline operates in much the same way as the laundry...
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Lec13 - System Specifications and Modeling Lecture 13 Last...

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