Lec19 - VERILOG HDL DESIGN Lec 19 © BITS Pilani Basic...

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Unformatted text preview: VERILOG HDL DESIGN Lec 19 © BITS, Pilani Basic concepts (F= in1 AND in2) //structural module AND2 (in1, in2, out); input in1; input in2; output out; wire in1, in2, out; and u1 (out, in1, in2); endmodule //dataflow module AND2 (in1, in2, out); input in1; input in2; output out; wire in1, in2, out; assign out = in1 & in2; endmodule //behavioral module AND2 (in1, in2, out); input in1; input in2; output out; wire in1, in2; reg out; always @(in1 or in2); out = in1 & in2; endmodule //Test fixture for AND2 module test_and2; reg i1, i2; wire o; AND2 u2 (i1, i2, o); initial begin i1 = 0; i2 = 0; #1 $display(“i1= %b i2= %b o= %b”, i1, i2, o); i1 = 0; i2 = 1; #1 $display(“i1= %b i2= %b o= %b”, i1, i2, o); i1 = 1; i2 = 0; #1 $display(“i1= %b i2= %b o= %b”, i1, i2, o); i1 = 1; i2 = 1; #1 $display(“i1= %b i2= %b o= %b”, i1, i2, o); end endmodule //Simulator output i1=0, i2=0, o=0 i1=0, i2=1, o=0 i1=1, i2=0, o=0 i1=1, i2=1, o=1 © BITS, Pilani...
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This note was uploaded on 05/08/2010 for the course EEE SSM taught by Professor Pawansharma during the Spring '10 term at Birla Institute of Technology & Science.

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Lec19 - VERILOG HDL DESIGN Lec 19 © BITS Pilani Basic...

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