Lec20 - VERILOG HDL DESIGN Lec 20 Another Example F = (in1...

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VERILOG HDL DESIGN Lec 20
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© BITS, Pilani Another Example F = (in1 AND in2) OR (in3 AND in4) //Structural module and_or (in1, in2, in3, in4, out); input in1, in2, in3, in4; output out; wire tmp; and #10 u1 (tmp, in1, in2), u2 (undec, in3, in4); or #20 (out, tmp, undec); endmodule //Data flow module and_or (in1, in2, in3, in4, out); input in1, in2, in3, in4; output out; wire tmp; assign #10 tmp = in1 & in2; wire #10 tmp1= in3 & in4; assign #20 out = tmp | tmp1; /*The three statements could be condensed */ into one //assign #30 out = (in1 & in2) | (in3 & in4); endmodule //Behavioral module and_or (in1, in2, in3, in4, out); input in1, in2, in3, in4; output out; reg out; always @(in1 or in2 or in3 or in4)   begin out = #30 1;   else out = #30 (in3 & in4);   end endmodule
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© BITS, Pilani Contd. . //Test fixture for and_or module module test_and_or reg r1, r2, r3, r4; wire o; and_or u2 (.in2(r2), .in1(r1), .in3(r3), .in4(r4), .out(o)); initial begin :b1   reg [4:0] i1234;   for ( i1234 = 0; i1234 < 16; i1234 = i1234 + 1) begin { r1, r2, r3, r4 } = i1234 [3:0]; #31 $display (“r1r2r3r4 = %b%b%b%b  o = %b”, r1, r2, r3, r4, o);             end   end endmodule and_or simulation result r1r2r3r4 = 0000, o = 0 r1r2r3r4 = 0001, o = 0 r1r2r3r4 = 0010, o = 0 r1r2r3r4 = 0011, o = 1 r1r2r3r4 = 0100, o = 0
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Lec20 - VERILOG HDL DESIGN Lec 20 Another Example F = (in1...

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