Lec21 - VERILOG HDL DESIGN Lec 21 Delays /Example 1 module...

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VERILOG HDL DESIGN Lec 21
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© BITS, Pilani Delays //Example 1 module three_initial; initial $display("Initial Statement 1"); initial $display("Initial Statement 2"); initial $display("Initial Statement 3"); endmodule //Example 2 module three_initial_with_delay; initial #1 $display("Initial Statement 1"); initial $display("Initial Statement 2"); initial #2 $display("Initial Statement 3"); endmodule
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© BITS, Pilani Every statement in Verilog may have a delay before it is run. If we have three initial statements as in the module in Example 1, we know they will all start at time 0. But they must run in some order: Which one will run first? The model in Example 1 creates a race condition at time 0. If it is important to have the statements run in a particular order, you can introduce delays to control the order in which the statements are executed.
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© BITS, Pilani begin-end blocks Initial and always can have only one statement. However, you will often need more than a single statement in your design. The begin-end block allows a set of sequential statements to follow an initial or always statement. The statements in the begin-end block are sequential so we know the statements will execute in the order we would expect. In begin-end blocks, delays are additive. module initial_two_begin; initial begin #1 $display("Statement 1"); $display("Statement 2"); #2 $display("Statement 3"); end initial begin $display("Block 2 Statement 1"); #2 $display("Block 2 Statement 2"); #2 $display("Block 2 Statement 3"); end endmodule Block 2 Statement 1  Statement 1  Statement 2  Block 2 Statement 2 Statement 3 Block 2 Statement 3
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© BITS, Pilani fork-join blocks The fork-join block is similar to the begin-end block. In
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This note was uploaded on 05/08/2010 for the course EEE SSM taught by Professor Pawansharma during the Spring '10 term at Birla Institute of Technology & Science.

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Lec21 - VERILOG HDL DESIGN Lec 21 Delays /Example 1 module...

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