Lec22 - VERILOG HDL DESIGN Lec 22 BITS, Pilani Timing...

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Unformatted text preview: VERILOG HDL DESIGN Lec 22 BITS, Pilani Timing delays module code11 (out1, out2, in); output out1, out2; input in; reg out1, out2; always @(in) begin #25 out1 = ~in; #40 out2 = ~in; end endmodule An always block that does not schedule events in zero time could miss RTL- or behavioral model triggered events. First, once the always block is entered due to a change on the sensitivity list variable in , subsequent changes on in will not cause re-entry until the always block is exited 65 time units later. Second, after a delay of 25 time units, the current value of in is read, inverted, and assigned to out1 . After an additional 40 time units, in will again be read, inverted, and assigned to out2 . During the timing delays, all other events on in will be ignored. The outputs will not be updated on every input change if changes happen more frequently than every 65 time units. The post-synthesis gate-level model will simulate two inverters while the pre- synthesis RTL code will miss multiple input transitions Placing delays on the left side of always block assignments does not accurately model either RTL or behavioral models. BITS, Pilani Blocking and Nonblocking assignments A Verilog race condition occurs when two or more statements that are scheduled to execute in the same simulation time step, would give different results when the order of statement execution is changed, as permitted by the Verilog Standard Execution of blocking assignments is a one-step process: Evaluate the RHS (right-hand side argument) and update the LHS (lefthand side argument) of the blocking assignment without interruption from any other Verilog statement "Blocks" trailing assignments in the same always block from occurring until after the current assignment has completed Execution of nonblocking assignments can be viewed as a two-step process:...
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This note was uploaded on 05/08/2010 for the course EEE SSM taught by Professor Pawansharma during the Spring '10 term at Birla Institute of Technology & Science.

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Lec22 - VERILOG HDL DESIGN Lec 22 BITS, Pilani Timing...

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