Lec23 - VERILOG HDL DESIGN Lec 23 Tasks and Functions Tasks...

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VERILOG HDL DESIGN Lec 23
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Tasks and Functions Tasks and functions provide the ability to execute common procedures from several different places in a description. They also provide a means of breaking up large procedures into smaller ones to make it easier to read and debug the source descriptions.
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Tasks task identifier; parameter_declaration; input_declaration; output_declaration; inout_declaration; register_declaration; event_declaration; statement; endtask
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A task can support multiple goals and can calculate multiple result values. However, only the output or inout type arguments pass result values back from the invocation of a task.
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A task can contain zero or more behavioral statements, e.g. case statement, if statement. A begin-end block is required for bracketing multiple statements. The task enabling statement should be made up of a task identifier and the list of comma- separated task arguments.
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The list of task arguments should be enclosed in parenthesis. If the task does not contain any argument declarations, then it should be enabled by specifying its identifier followed by a semicolon.
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The list of task enabling arguments should correspond exactly to the list of task arguments. If a task argument is declared as an input, then a corresponding argument of the task enabling statement can be any expression.
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If a task argument is declared as an output or an inout then the corresponding argument of the task enabling statement should be one of the following items: Register data types Memory references Concatenations of registers or memory references Bit-selects and part-selects of reg, integer and time registers
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The following rules distinguish tasks from functions: A function shall execute in one simulation
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This note was uploaded on 05/08/2010 for the course EEE SSM taught by Professor Pawansharma during the Spring '10 term at Birla Institute of Technology & Science.

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Lec23 - VERILOG HDL DESIGN Lec 23 Tasks and Functions Tasks...

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