Lec24 - VERILOG HDL DESIGN Lec 24 FSM Design FSM...

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VERILOG HDL DESIGN Lec 24 FSM Design
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FSM classification
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FSM coding goals The FSM coding style should be easily modified to change state encodings and FSM styles. The coding style should be compact. The coding style should be easy to code and understand.
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The coding style should facilitate debugging. The coding style should yield efficient synthesis results.
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State Encoding (binary or one-hot) A binary-encoded FSM design only requires as many flip-flops as are needed to uniquely encode the number of states in the state machine. A onehot FSM design requires a flip-flop for each state in the design and only one flip-flop (the flip-flop representing the current or "hot" state) is set at a time in a onehot FSM design.
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Two always-block coding style One of the best Verilog coding styles is to code the FSM design using two always blocks, one for the sequential state register and one for the combinational next-state and combinational output logic.
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Example module fsm_cc4
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This note was uploaded on 05/08/2010 for the course EEE SSM taught by Professor Pawansharma during the Spring '10 term at Birla Institute of Technology & Science.

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Lec24 - VERILOG HDL DESIGN Lec 24 FSM Design FSM...

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