01ece108HWset1 - Esener ece108 HW set 1 Problem#1 Problem#2...

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Unformatted text preview: Esener ece108 HW set 1 Problem #1 Problem #2 1 Problem #3 Problem #5 Show that the parallel connection of MOSFETs shown below behaves as a single MOSFET with a width equal to the sum onf the individual MOSFET widths Problem #5 Problem #6 Show that the the bottom MOSFET in the Figure below in a series connection fo two MOSFETS cannot operate in saturation region. Neglect the body effect. Problem #7 A hypothetical two terminal device with IV characteristics as shown in figure 1a is considered for use as a pull up device for an inverter. The device is not affected by body effect and occupies the same size as a comparable PMOS device and can be integrated with NMOS devices on the same substrate. The inverter pull down is a conventional NMOS transistor with a threshold voltage of . Draw the load line associated with this pull-up on the output characteristics in figure 1b. Plot the voltage transfer characteristics of such an inverter by carefully showing critical voltage values on the plot. Determine the input voltage for which the transfer characteristics have maximum slope (sharpest transition). What is the maximum output high and minimum output low voltage that this inverter can exhibit? What is the output dynamic range? Is this a ratioed or ratioless inverter? What is the peak current that can flow in the circuit? Discuss qualitatively the performance of this logic capability with that of CMOS logic when driving similar load capacitance in terms of area consumed noise margins power dissipation Explain your answers. Problem #8 Depletion mode inverter design ...
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This note was uploaded on 05/09/2010 for the course EE 121 taught by Professor Cswe during the Spring '10 term at Punjab Engineering College.

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