hdl_for_asics - 5/11/10 Difference in ASIC and FPGA FPGA...

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Unformatted text preview: 5/11/10 Difference in ASIC and FPGA FPGA price effective for large volumes (10k+ parts) time to market dynamic specifications ASIC price effective for small volumes high speed 5/11/10 ASIC Design Flow { F 4 D 6 C 2 9 E -9 6 5 D -4 F E -A 9 1 E -F 0 E 1 7 C 9 1 4 B 9 E } RTL Coding & Verification { 3 E B 7 5 A F B -D 9 C 7 -4 2 7 4 -8 F 0 C -4 7 9 A 2 3 D 9 0 2 7 5 } Synthesis { 0 5 D D 1 5 D -1 4 1 7 -4 F 0 2 -A 1 9 A -5 3 6 E 1 3 A 8 4 1 B 9 } Floor plan { A B 8 E B 8 7 -1 7 D 3 -4 0 3 9 -A B 2 9 -F 0 D 8 5 E 6 D 0 3 F 0 } DFT insertion & ATGP (o { 0 8 F E 2 5 C F -7 6 9 3 -4 3 8 2 -8 F 2 9 -4 A E 5 6 1 C 2 1 F C 3 } Logic verification / STA { C 9 3 7 0 4 C -1 7 0 E -4 1 2 5 -B E 1 -B 6 B 0 E 6 3 9 0 6 3 E } Place & Route { 2 B 8 E E 7 D -9 A 9 2 -4 F 4 6 -8 4 B 7 -E C A C 0 4 3 5 1 } Sign-off verification DFT (Design For Test) - p E & PE e& && *& * . ATPG(Auto Test Pattern Group)- human fail @ m* * 9 * tool N & . (Tet- raMax tool ) STA(Static Timing Analysis)- 1,0 * Clock Inform @ m * ....
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hdl_for_asics - 5/11/10 Difference in ASIC and FPGA FPGA...

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