7 MOST 10

7 MOST 10 - The MOS transistor Our goal is to exploit...

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Unformatted text preview: The MOS transistor Our goal is to exploit scaling opportunities but Who needs it? Can they (or we) afford it? How do we do it? P erformance, P rice and P hysics ! Even More The exploitation of Metal-Oxide- Semiconductor transistors Now that we know something about the starting material and basic sub-structures, what do we do with them? The exploitation of silicon continues with an exploitation of the kings of active devices, M etal O xide S emiconductor Transistors! While you are studying this lecture, try to think how processing will affect device parameters! More likely doped poly-Si! Capacitance: C ox = ox o t ox . L . W MOS Capacitor the gate-channel region W L t ox Si Simplified gate capacitance What is the dielectric constant for SiO 2 ?- - - - - - - - - - + + + + + + + + Induced charge: Q c = C ox . V g Gate bias effects + V g- V g Charge - Q c Charge + Q c Completion of the transistor structure Add dopant to adjust channel region to required dopant level (done before we put the gate on) Add source and drain contacts as source of carriers in channel (done after we put the gate on) Bias drain to move carriers in channel Bias gate to control channel conduction- - - - - - - - - - n+ n+ p Si substrate + V g + V d Drain Source Ground Called the V t adjust implant Practical device threshold + Vg Id Vt Logic 0 region Implant positive charge in channel so the condition V g > V t must be met before any drain current flows!- - - - - - - - - - n+ n+ p-Si substrate + V g + V d Drain Source Ground Logic 1? +Vdd Output, Vd Vg, Input Typical bias conditions Lo/Hi Hi/Lo Digital Analog/driver +Vdd Output, Vd Vg 1. Zero bias 2. Digital Off V g < V t V d ~ V dd 3. Digital On V g >> V t V d ~ 0 4. Analog V t < V g > V d Well look at all these cases in the following slides Case 1 - zero bias p n + Band diagram V g = 0 n + V d = 0 V s = 0 depletion layer, w L eff Scale: 1 V/div Effective channel length Small-geometry effects The effective length is always going to be smaller than the drawn length due to the depletion region . We cannot afford to create an extremely short channel due to this....
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7 MOST 10 - The MOS transistor Our goal is to exploit...

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