8 Processing 10

8 Processing 10 - Processing Our goal is to exploit scaling...

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Processing Our goal is to exploit scaling opportunities but… Who needs it? Can they (or we) afford it? How do we do it? P erformance, P rice and P hysics With some solid Engineering !
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The exploitation of processing We now know a lot about: Materials Devices Markets Applications The Roadmap … Now, what must we do to make the product? n-well p-well We’ll review: Critical dimensions Power dissipation Isolation How to construct a process Engineerin g stuff!
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Most basic device fabrication sequence Grow thick oxide on silicon Etch rectangle Grow gate oxide Deposit and pattern gate Diffuse source/drain Gate acts as mask ( self-aligned gate) Top view Side view
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More realistic target structure p-channel n-channel
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Control dimensional parameters W is determined by thick oxide edge L is set by gate dimension Gate oxide needs to be uniform across W dimension ( 29 I t W L V V V V d ox o ox d g t d = - - κεμ . . 2 2 W L t ox W
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Parameter control at 100 nm – W/L W Transition from thick to thin oxide must be gradual for good gate step coverage (but z-scaling helps). So W is fuzzy. Diffusion under gate edge gives L eff < L (use SPACERS ) Gate oxide is generally uniform (except at edge!) but it is very thin W L L eff
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Effective device width W eff Poly Field oxide Gate oxide Channel - flow into paper Gradual change in oxide thickness is a result of the LOCOS process – discussed later…
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Threshold voltage – 5 components 1. Surface potential 2. Gate-channel work function 3. Depletion layer charge 4. Fixed interface charge 5. Implanted charge (Note that threshold voltage is also affected by substrate bias
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This note was uploaded on 05/11/2010 for the course EEE EEE-530 taught by Professor Kozicki during the Spring '10 term at ASU.

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8 Processing 10 - Processing Our goal is to exploit scaling...

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