16 Interconnect 10

16 Interconnect 10 - Interconnect This lecture covers...

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Multiple levels of metal allow more ways for the circuit to be wired This leads to greater design flexibility and enhanced circuit functionality However, interconnect can also be a limit to circuit performance due to parasitics ! Interconnect This lecture covers advanced interconnect technologies and multi-level metal (MLM) schemes…
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The story so far… Systems/economics Devices/scaling Unit processes Cleaning Diffusion Oxidation CVD Implant Etch Sputter Interconnect Litho (2) Wafer finishing Done! Now what? well Fox
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Oxide n-well p-well Advanced interconnect structure Multi-level interconnect is driving the industry! Technolog y R & D Products Profit How many levels of interconnect do we have here? Increasing numbers of interconnect levels have opened up new design possibilities
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Interconnect requirements Memory - use diffusion, 2 poly, 2 metal Optimized cell 4 I/O lines ~10 8 identical Cells + Relatively small area for I/O Multiplex access 20 - 60 package I/O Logic - needs fast signal propagation across whole chip low RC paths and > 2 layer metal Optimized gate 4 - 16 I/O lines >10 5 gates many types Many fan-out paths 140 - 600 package I/O
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Interconnect functional blocks Chip-level X, Y, Power Library block X, Y Cell block X, Y (can also use poly or 1st metal) Example 2.5 V, 25 W 10A supply! 200 V dd pins 200 Ground pins 200 signal pins We need layers of interconnect for various functions…
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This side is mostly logic arrays with 2 layers per gate and 2 layers for interconnect. This side is mostly memory arrays with simpler design of interconnect On top of all this, super- impose x & y paths for signal and power Example - a microprocessor
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Packing density (k transistors/mm 2 ) Technology evolution - packing density 0.1 1 10 100 1000 1965 1970 1975 1980 1985 1990 1995 2000 DRAM Processor Slope: CD -2 Advent of 4-6 layer metal Concept Process Memory Interconnect System Drivers
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General interconnect requirements Minimize signal delay Good uniformity and topography Operate at minimum CD Optimized materials combinations Planar surfaces lecture 19 Yield lecture 9 Ohmic contacts lecture 6 Barrier layers lecture 15 Low failure probability lecture 21 Done!
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This note was uploaded on 05/11/2010 for the course EEE EEE-530 taught by Professor Kozicki during the Spring '10 term at ASU.

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16 Interconnect 10 - Interconnect This lecture covers...

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