22 CMOS 10

22 CMOS 10 - Basic CMOS Process Flow This lecture...

Info iconThis preview shows pages 1–11. Sign up to view the full content.

View Full Document Right Arrow Icon
1 Basic CMOS  Process Flow This is a generic process.  Any link to any commercial process is coincidental This lecture highlights the architecture and  main steps for a basic CMOS process flow  (courtesy of Dr. John Robertson of ASU Poly). 1.    Substrate preparation 2.    Isolation 3.    Device formation 4.    Interconnect Outline
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 Target device structure This should be familiar now
Background image of page 2
3 Process flow Follow typical sequence for # 1  -  4
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
4 Silicon p-type substrate Starting material: 150 mm or 200 mm diameter wafer <100> orientation 18  cm resistivity Check specification Laser mark Clean Grow 40 nm  pad oxide LPCVD 120 nm silicon nitride Note:  We shall not show any cleaning steps even though they may remove some surface layers Expansion coefficient of nitride > silicon Oxide pad layer acts as plastic buffer for stress relief.
Background image of page 4
5 Adaptations Even at this stage, smaller geometry processes have modifications: •  Damage back side of wafer and anneal to     accumulate lattice defects and impurities at back •  Anneal in nitrogen to drive oxygen impurities     deep into the Si where they can cluster on other    defect sites -  denuded zone (DZ)  process •  Start with lightly doped epi layer on heavily    doped substrate for latch-up suppression
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
6 1st Photo step;   spin 0.8 micron positive resist.   Dark field (DF) mask Define n-well Develop image Photoresist p-substrate Pad oxide Silicon nitride D wm Mask image representation Assume ideal image projection on resist Use positive resist throughout the sequence
Background image of page 6
7 p-substrate n-well Implant P +    medium dose:   6e12 cm -2 Develop resist Plasma etch silicon nitride (good resolution) Implant dopant for n-well using resist as a mask (Remove resist) Why leave the oxide layer? What happens here?
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
8 Lateral oxide growth Nitride Oxide Oxygen diffusion during  thermal growth Silicon Result: Nitride bends up and oxide encroaches under nitride film What factors might determine the oxide and nitride layer thicknesses?
Background image of page 8
9 p-substrate n-well Grow thermal oxide, 300 nm, where surface is not protected by nitride layer. Oxidizing ions diffuse under edges of nitride and push up film.  Well dopant diffuses down and laterally. Balance nitride thickness: Thicker may crack brittle film Thinner gives too much edge offset. 300 nm Note:  First of many trade-offs
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
10 Wet etch to remove silicon nitride layer Blanket boron implant to dope p-well (Higher concentration than background doping in p-type substrate). Select energy so ions penetrate thin (40 nm ) pad oxide 
Background image of page 10
Image of page 11
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 05/11/2010 for the course EEE EEE-530 taught by Professor Kozicki during the Spring '10 term at ASU.

Page1 / 54

22 CMOS 10 - Basic CMOS Process Flow This lecture...

This preview shows document pages 1 - 11. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online