Nanotech_in_logic_apps - Benchmarking Nanotechnology for...

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Benchmarking Nanotechnology for High-Performance and Low- Power Logic Transistor Applications Robert Chau Components Research, Logic Technology Development, Intel Corporation Address: 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124, USA (Mailstop RA3-252) E-mail address: [email protected] Abstract — Recently there has been tremendous progress made in the research of novel nanotechnology for future nanoelectronics applications. In particular, several novel nanoelectronic devices such as carbon-nanotube field effect transistor (FET), Si nanowire FET, and planar III-V compound semiconductor FET, all hold promise as device candidates to be integrated onto the silicon platform for enhancing circuit functionality and also for extending Moore’s Law. For high-performance and low-power logic transistor applications, it is important that these research devices are frequently benchmarked against the existing Si logic transistor data in order to gauge the progress of research. In this work, we compare these novel nanoelectronic devices to the state-of-the-art planar and non- planar Si logic transistors in terms of intrinsic speed, energy- delay product, and electrostatics. The results of this benchmarking exercise indicate that while these novel nanoelectronic devices show promise and opportunities for future logic applications, their device characteristics and electrostatics still need to be improved. We believe that BENCHMARKING is a key element in accelerating the progress of nanotechnology research for logic transistor applications. Index Terms Nanotechnology, semiconductor devices, carbon nanotubes. I. INTRODUCTION Moore’s Law states that the number of transistors per integrated circuit doubles every 24 months, and it has been the guiding principle for the semiconductor industry for over 30 years. The sustaining of Moore’s Law requires transistor scaling, as illustrated in Figure 1. The physical gate length ( L g ) of the Si transistor used in our present 90 nm generation node is ~50 nm. It is projected that the size of the transistor will reach ~10 nm in 2011. Through technology innovations, such as, strained-Si channels [1], [2], metal-gate/high-K stacks [3], [4], and the non-planar fully-depleted Tri-gate CMOS transistor architecture [5], [6], Moore’s Law will continue at least through early next decade. By combining silicon innovations with other novel nanotechnologies on the same silicon platform, we expect Moore’s Law will be extended well into the next decade. Recently, there has been tremendous progress made and excitement generated in the research of novel nanotechnology for future nanoelectronics applications. To gauge the progress of research for high-performance and low-power logic applications, it is important that these new devices be benchmarked against the best Si MOSFET data using a set of metrics commonly used by the semiconductor industry. In this work, we compare several novel nanoelectronic devices, including carbon-
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This note was uploaded on 05/11/2010 for the course EEE EEE-530 taught by Professor Kozicki during the Spring '10 term at ASU.

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Nanotech_in_logic_apps - Benchmarking Nanotechnology for...

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