CSE230_Set02_Instructions - CSE 230 Computer Organization...

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CSE 230 Computer Organization and Assembly Language Fall 2006 Computer Science & Engineering Department Arizona State University Tempe, AZ 85287 Instructor: Dr. Baoxin Li [email protected] Office: Brickyard 502
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set 2 -- 2 Chapter 2 – Instruction Set Program instruction operation Design of an instruction set : simplicity for implementation representing the primitives in high-level language Programmer’s view: operation + operand (s) Computer’s view: binary instructions with a specific format ADD A, B, C SUBTRACT C, D, E AND A, C, E OR . . . COMPARE A, B . . 01010 . . . . 01110 . . . . 10011 . . . . 10001 . . . . 11010 . . . . . .
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set 2 -- 3 Von Neumann Architecture Data and Instructions mixed in same memory ("stored program computer") Program as data (dubious advantage) Storage utilization Single memory interface Harward architecture data & instructions in separate memories may have advantages in certain applications CPU Memory I/O Computer Program (Instructions)
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set 2 -- 4 Instructions are bits Programs are stored in memory — to be read or written just like data Fetch & Execute Cycle Instructions are fetched and put into a special register Bits in the register "control" the subsequent actions Fetch the “next” instruction and continue Processor Memory memory for data, programs, compilers, editors, etc. Stored Program Concept
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set 2 -- 5 What Must Be Specified ? Instruction Format or Encoding how is it decoded? Location of operands and result where other than memory? how many explicit operands? how are memory operands located? which can or cannot be in memory? Data type and Size Operations what are supported Successor instruction jumps, conditions, branches Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction
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set 2 -- 6 MIPS Arithmetic All instructions have 3 operands Operand order is fixed (destination first) Example: C code: a = b + c + d MIPS ‘code’:add a, b, c add a, a, d “The natural number of operands for an operation like addition is three…requiring every instruction to have exactly three operands, …. keeping the hardware simple” Operands must be registers, only 32 registers in MIPS Each register contains 32 bits Design Principle: smaller is faster. Why?
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set 2 -- 7 Arithmetic and Logical Instructions 3 operands (2 sources and 1 destination) add $1, $2, $3 # (reg_2 + reg_3) reg_1 An alternative (2 operand: the 1st source is also the destination) sub $1, $2 # (reg_1 - reg_2) reg_1 add (+), addu, sub(-), subu, mult(*), multu, div(/), divu, and, or, nor, xor, sll, sllv, sra, srav, srl, srlv (shift) Instruction format: R -type op rs rt rd shamt funct add $1, $21, $29: 000000 10101 11101 00001 00000 100000
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set 2 -- 8 Registers Internal storage of CPU that can be controlled by programs as operands of instructions general purpose (data or address) or special purpose small (few) and fast : $0 - $31 --- 32 registers (5-bit address) reduce memory traffic (operands are in CPU) easy to address (few bits of address ) - improve code density add reg1 and reg2, save the result in reg3 add M(1000) and M(2000),save to M(3000) Memory registers ALU CPU
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