CSE230_Set05_Processor

# CSE230_Set05_Processor - CSE230/EEE230 Computer...

This preview shows pages 1–13. Sign up to view the full content.

Arizona State University Tempe, AZ 85287 Instructor: Dr. Baoxin Li [email protected] Office: Brickyard 502 CSE230/EEE230 Computer Organization and Assembly Language Fall 2006

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
2 Build An ALU We will build a basic processor in Chapter 5 First, a brief review on Boolean logic and the ALU (material from Appendix B) 32 32 32 operation result a b ALU
3 Problem: Consider a logic function with three inputs: A, B, and C. Output D is true if at least one input is true Output E is true if exactly two inputs are true Output F is true only if all three inputs are true Show the truth table for these three functions. Show the Boolean equations for these three functions. Show an implementation consisting of inverters, AND, and OR gates. Review: Boolean Algebra & Gates

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
4 Let's build an ALU to support the and and or instructions we'll just build a 1 bit ALU, and use 32 of them Possible Implementation b a operation result op a b res An ALU (arithmetic logic unit)
5 Select one of the inputs to be the output, based on a control input S C A B 0 1 Review: Multiplexor note: we call this a 2-input mux even though it has 3 inputs!

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
6 Not easy to decide the “best” way to build something Don't want too many inputs to a single gate Don’t want to have to go through too many gates for our purposes, ease of comprehension is important Let's look at a 1-bit ALU for addition: How could we build a 1-bit ALU for add, and, and or? Different Implementations c out = a b + a c in + b c in sum = a xor b xor c in Sum CarryIn CarryOut a b
7 Building a 32 bit ALU b 0 2 Result Operation a 1 CarryIn CarryOut Result31 a31 b31 Result0 CarryIn a0 b0 Result1 a1 b1 Result2 a2 b2 Operation ALU0 CarryIn CarryOut ALU1 CarryIn CarryOut ALU2 CarryIn CarryOut ALU31 CarryIn

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
8 Two's complement approach: just negate b and add. A very clever solution: What About Subtraction (A – B) ? 0 2 Result Operation a 1 CarryIn CarryOut 0 1 Binvert b
9 Adding a NOR function Can also choose to invert a. How do we get “a NOR b” ? Binvert a b CarryIn CarryOut Operation 1 0 2 + Result 1 0 Ainvert 1 0

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
10 Need to support the set-on-less-than instruction (slt) remember: slt is an arithmetic instruction produces a 1 if rs < rt and 0 otherwise use subtraction: (a-b) < 0 implies a < b Need to support test for equality (beq \$t5, \$t6, \$t7) use subtraction: (a-b) = 0 implies a = b Tailoring the ALU to the MIPS
11 Supporting slt Binvert a b CarryIn CarryOut Operation 1 0 2 + Result 1 0 Ainvert 1 0 3 Less Binvert a b CarryIn Operation 1 0 2 + Result 1 0 3 Less Overflow detection Set Overflow Ainvert 1 0 Use this ALU for most significant bit all other bits

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
a0 Operation CarryIn ALU0 Less CarryOut b0 CarryIn a1 CarryIn ALU1 Less CarryOut b1 Result0 Result1 a2 CarryIn ALU2 Less CarryOut b2 a31 CarryIn ALU31 Less b31 Result2 Result31 . . . . . . . . . Binvert
This is the end of the preview. Sign up to access the rest of the document.

## This note was uploaded on 05/11/2010 for the course CSE/EEE CSE/EEE230 taught by Professor Baoxinli during the Fall '08 term at ASU.

### Page1 / 66

CSE230_Set05_Processor - CSE230/EEE230 Computer...

This preview shows document pages 1 - 13. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online