CSE230_Set06_Pipelining

CSE230_Set06_Pipelining - CSE230/EEE230 Computer...

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Computer Science & Engineering Department Arizona State University Tempe, AZ 85287 Instructor: Dr. Baoxin Li baoxin.li@asu.edu Office: Brickyard 502 CSE230/EEE230 Computer Organization and Assembly Language Fall 2006
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2 Chapter 6 Enhancing Performance with Pipelining An Overview of Pipelining (Section 6.1) A Pipelined Datapath (Section 6.2) Advanced Pipelining (Section 6.9) Real Stuff: The Pentium 4 Pipeline (Section 6.10)
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3 The Laundry Analogy
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4 How Much Faster Can We Get? Potential Speedup? The number of stages Note: the execution time for a single task (instruction) is not improved What improved is the overall throughput (# of instructions) What if different stages take different amount of time? Must accommodate the worst case; lower the speed The start-up and wind-down’s affect on performance Significant if the number of tasks is not large compared to the number of stages Insignificant if the number of task is much larger than the number of stages
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5 Recall: The multi-cycle MIPS processor CYCLE 1 2 3 4 5 R-type A op B ALUout Rd Η ALUout LW A op Ext[IR[15- 0]] Η ALUout (memory read) M-data Mem[ALUout] Rd h&& M-data SW A op Ext[IR[15- 0]] ALUout (memory write) Mem[ALUout] B beq if (A==B) PC Target Jump IR && &&Mem[PC] PC Η PC+4 A Ext[IR[25-21]] B Ext[IR[20-16]] Ext[IR[15-0]] Target PC+ SigExt[IR[15-0]]*4 PC PC[31:28]|(IR[25: 0]<<2)
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6 The Five Stages of lw Instruction Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Ifetch Reg/Dec Exec Mem Wr Load Assume that 1. instruction memory read takes 200ps 2. register read : 100ps 3. exec: 200ps 4. data memory access: 200ps 5. reg. write: 100ps With a 5GHz clock, the total execution time of 5 cycles: 1ns
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7 Single-Cycle versus Pipelined Performance
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8 MIPS: Designed for Pipeline Is MIPS well posed for pipelining? All MIPS instructions are the same length Has only a few instruction formats Memory operands only appear in loads and stores Operands must be aligned in memory
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9 Pipeline Hazards Pipelining is nice, but … Structural Hazards The hardware cannot support the combination of instructions that we want to execute in the same clock cycle.
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CSE230_Set06_Pipelining - CSE230/EEE230 Computer...

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