FMP6 - For More Practice FMP 6.14-1 For More Practice...

Info iconThis preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon
For More Practice FMP 6.14-1 For More Practice Understanding Pipelines by Drawing Them 6.7 [5] <§6.2> On page 396, we gave the example code sequence: lw $10, 20($1) sub $11, $2, $3 Figures 6.19 on page 397 and 6.20 on page 397 showed the multiple-clock-cycle pipeline diagrams for this two-instruction sequence executing across 6 clock cycles. Figures 6.14.1 through 6.14.3 show the corresponding single-clock-cycle pipeline diagrams for these two instructions. Note that the order of the instruc- tions differs between these two types of diagrams: the newest instruction is at the bottom and to the right of the multiple-clock-cycle pipeline diagram, and it is on the left in the single-clock-cycle pipeline diagram. In the following three exercises, use the following code sequence: add $4, $2, $3 sw $5, 4($2) For the above code sequence, draw the multiple-clock-cycle pipeline diagram using the format shown in Figure 6.19 on page 397. 6.8 [5] <§6.2> For the code sequence in Exercise 6.7, draw the multiple-clock- cycle pipeline diagram using the format shown in Figure 6.20 on page 397. 6.9 [15] <§6.2> For the above code sequence show the pipeline over 6 clock cycles using the single-clock-cycle diagrams, as in Figures 6.14.1 through 6.14.3. Figure 6.14.4 has a blank single-clock-cycle pipeline diagram that may be reproduced to ease your task!
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
FMP 6.14-2 For More Practice FIGURE 6.14.1 Single-cycle pipeline diagrams for clock cycles 1 (top diagram) and 2 (bottom diagram). This style of pipeline representation is a snapshot of every instruction executing during 1 clock cycle. Our example has but two instructions, so at most two stages are identiFed in each clock cycle; normally, all Fve stages are occupied. The highlighted portions of the datapath are active in that clock cycle. The load is fetched in clock cycle 1 and decoded in clock cycle 2, with the subtract fetched in the second clock cycle. To make the Fgures easier to understand, the other pipeline stages are empty, but normally there is an instruction in every pipeline stage. Instruction memory Address 4 32 Instruction IF/ID EX/MEM MEM/WB Add Add PC Registers Read data 1 Read data 2 Read register 1 Read register 2 16 Sign extend Write register Write data ID/EX Instruction decode lw $10, 20($1) Instruction fetch sub $11, $2, $3 Instruction memory Address 4 32 Add Add result Shift left 2 Shift left 2 IF/ID EX/MEM PC Write data Registers Read data 1 Read data 2 Read register 1 Read register 2 16 Write register Write data Read data ALU result ALU Zero Add Add result ALU result ALU Zero ID/EX Instruction fetch lw $10, 20($1) Address Data memory Write data Read data Address Data memory Clock 1 Clock 2 M u x 0 1 M u x 0 1 M u x 0 1 M u x 1 0 M u x 1 0 M u x 0 1 Sign extend MEM/WB
Background image of page 2
For More Practice FMP 6.14-3 FIGURE 6.14.2 Single-cycle pipeline diagrams for clock cycles 3 (top diagram) and 4 (bottom diagram). In the third clock cycle in the top diagram, lw enters the EX stage. At the same time, sub enters ID.
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 4
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 05/11/2010 for the course CSE/EEE CSE/EEE230 taught by Professor Baoxinli during the Fall '08 term at ASU.

Page1 / 22

FMP6 - For More Practice FMP 6.14-1 For More Practice...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online