HW5-Grading Policy

HW5-Grading Policy - 6.3 See the following figure: 6.4...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
6.1 a. Shortening the ALU operation will not affect the speedup obtained from pipelining. It would not affect the clock cycle. b. If the ALU operation takes 25% more time, it becomes the bottleneck in the pipeline. The clock cycle needs to be 250 ps. The speedup would be 20% less. 6.2 a. It takes 100 ps * 10 6 instructions = 100 microseconds to execute on a nonpipelined processor (ignoring start and end transients in the pipeline). b. A perfect 20-stage pipeline would speed up the execution by 20 times. c. Pipeline overhead impacts both latency and throughput.
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 2
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 6.3 See the following figure: 6.4 There is a data dependency through $3 between the first instruction and each subsequent instruction. There is a data dependency through $6 between the lw instruction and the last instruction. For a five-stage pipeline as shown in Figure 6.7, the data dependencies between the first instruction and each subsequent instruction can be resolved by using forwarding. The data dependency between the load and the last add instruction cannot be resolved by using forwarding. 6.7 6.8...
View Full Document

This note was uploaded on 05/11/2010 for the course CSE/EEE CSE/EEE230 taught by Professor Baoxinli during the Fall '08 term at ASU.

Page1 / 2

HW5-Grading Policy - 6.3 See the following figure: 6.4...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online