The Chinese University of Hong Kong
Department of Computer Science and Engineering
ERG2020A (Fall 2007): Revision Exercise # 4
1. (420) A serial two’s complementer is to be designed. A binary integer of arbitrary
length is presented to the serial two’s complementer least significant bit first on input
X. When a given bit is presented on input X, the corresponding output bit is to appear
during the same clock cycle on output Z. To indicate that a sequence is complete and
that the circuit is to be initialized to receive another sequence, input Y becomes 1 for
one clock cycle. Otherwise, Y is 0.
Design your circuit using D flipflops and JK flipflops. State table and logic diagrams
must be shown.
2. Implement a pattern recognizer for the pattern: 110011 by D FFs.
3. Design a counter which counts in the sequence 0,2,1,3 and repeats.
Hint:
Treat
this as a twooutput, zeroinput, finite state machine whose outputs are the count in
binary.
State transitions occur on clock pulses.
Show the state diagram and show
implementations using: (a) D FFs, (b) JK FFs, (c) T FFs.
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 Spring '07
 LeeKinHong
 Computer Science, Binary numeral system, Decimal, Binarycoded decimal, Least significant bit, Chinese University of Hong Kong Department of Computer Science and Engineering

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