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Unformatted text preview: The Chinese University of Hong Kong Department of Computer Science and Engineering ERG2020A (Fall 2007): Revision Exercise #4 Suggested Solution 1. (420) A serial two’s complementer is to be designed. A binary integer of arbitrary length is presented to the serial two’s complementer least significant bit first on input X. When a given bit is presented on input X, the corresponding output bit is to appear during the same clock cycle on output Z. To indicate that a sequence is complete and that the circuit is to be initialized to receive another sequence, input Y becomes 1 for one clock cycle. Otherwise, Y is 0. (a) Find the state diagram for the serial two’s complementer. Assume Z goes 0 while Y = 1. 1 10/1 X1/X 10/0 00/1 00/0 X1/X XY/Z (b) Find the state table for the serial two’s complementer. Present State Inputs Next State Output FlipFlops inputs Q’ X Y Q Z D J K 1 X 1 1 X 1 1 X 1 X 1 1 1 X 1 1 X 1 1 1 X 1 1 1 X 1 X 1 1 1 X 1 1 1 1 1 X 1 X (You should also give both the implementations in D FFs and JK FFs. State tables and logic diagrams must all be shown.) [20 pts] Using D FlipFlops, give following Kmaps 1 1 Q’ X Y 1 1 1 D = Y + Q X 1 Using JK FlipFlops, give following Kmaps J K Q’ X Y 1 X X X X 1 Q’ X Y 1 X X X X J = Y K = X Y Z Q’ X Y 1 X X X X 1 Z = X Q + XQ = X Q 2 Logic Diagram using D FlipFlops D Q Q Q Q’ Y X CLK Z Logic Diagram using JK FlipFlops J Q Q K Y X Q Q’ Z CLK 2. Implement a pattern recognizer for the pattern: 110011 by D FFs. [15 pts] 000 001 010 011 100 101 0/0 1/0 1/0 1/0 0/0 0/0 1/0 1/1 0/0 0/0 1/0 0/0 3 Present State Input Next State Output A B C X A B C Z 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1...
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 Spring '07
 LeeKinHong
 Computer Science

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