tutorial9 - ERG2020A Tutorial 9 Sequential System Design...

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ERG2020A Tutorial 9 Sequential System Design Examples [Complete Version]
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2 Timing Analysis [CSC1410 96-97 Q7] Complete the waveform Y1 and SYNOUT for the given sequential circuit CK ASYNIN Y 1 SYNOUT S R D C ASYNIN Y 1 SYNOUT CK
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3 Solution CK ASYNIN Y 1 SYNOUT S R D C ASYNIN Y 1 SYNOUT CK Latch sensitive to levels at inputs Flip-flop sensitive to clock edge
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4 [CSC1410 00-01 Q3] Draw a state diagram for the state machine whose behaviour is summarised in the following state (excitation) table. Don’t forget to show the don’t care terms. Marks will be deducted if “d’s” are not used at the appropiate arcs. (8%) Present State Present input X1 X0 S1 S0 00 01 10 11 0 0 A D/1 D/1 A/0 A/1 0 1 B C/1 C/1 B/1 A/1 1 0 C B/1 B/1 C/0 C/0 1 1 D A/1 C/0 A/0 C/0 Design the finite state machine using simple edge trigged D-type flip flops. Solve the two characteristic equations (Y1, Y0) for the next state and the output equation Z. Sketch the design. (8%)
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Solution A D
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This note was uploaded on 05/18/2010 for the course ENGINEERIN ERG2020A taught by Professor Leekinhong during the Spring '07 term at CUHK.

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tutorial9 - ERG2020A Tutorial 9 Sequential System Design...

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