tutorial10 - ERG2020A Tutorial 10 Lab 3 Review Lab 4...

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ERG2020A Tutorial 10 Lab 3 Review Lab 4 Preparation: 6264 8k x 8 RAM
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2 Lab 3: 1-heap Nim Implementation Procedure: FSM design State table simplication Circuit implementation Simulation Implementation Testing Happens at Quiz and Exams! Impressive memory!
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3 FSM Design Mealy or Moore? How many states? (4, 8, 16) How many outputs of FSM? How to switch player? WAIT CHECK1 HALT CHECK2 d1d/HEAP_EN=1 dd1 dd1 1dd/HEAP_EN1 00d dd0/HEAP_EN=1 dd0/SWITCH_PL=1 [BTN1][BTN2][WIN]/[ACTION]
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4 State Table Simplication Espresso is reliable. Check if your state table covers all input cases. Make reasonable assumptions (e.g. BTN pulse, exclusive BTN, etc)
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5 Circuit Implementation Preferred: put your FSM into a module
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6 Inside the FSM module Decoder D Flip-flop T Flip-flop More….
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7 Useful Tools F7: Query Window Check connections, search nets Ctrl-H: Hierarchy Push Load you in the module (and load you out) Options Update Simulation Options Simulate Current Macro
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tutorial10 - ERG2020A Tutorial 10 Lab 3 Review Lab 4...

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