5.4 READY’ is an expression instead of a signal name, with ‘ being a unary operator. Use a name like READY_L or /READY instead. 5.5 In most logic technologies (including CMOS and TTL), inverting gates are faster and have fewer transistors than noninverting ones. Also, some signals must be created active-low in order to drive the predefined, active-low control inputs of MSI and LSI devices. 5.6 False. Connecting a bubble output to a non-bubble input(or vice versa simply means) that the input’s function is performed when the output signal is negated. This is perfectly alright if that’s how you want the circuit to operate. 5.7 Hierarchical, since only one copy of the network-port schematic need be drawn. You might say, “Well, I can make it non-hierarchical (flat), draw one original schematic page for one port, and copy it eleven more times.” There are two drawbacks to this approach: 1)You have to manually renumber the identifiers (reference designators and signal names) on each page to distinguish the ports.
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