Unit 4 - ERG 2020A Unit 4 Hardware Description Languages...

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1 ERG 2020A Unit 4 Hardware Description Languages Professor K.W.Cheung HSH 819 X 8348 kwcheung@ie.cuhk.edu.hk
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2 Outline • Why HDL ? • HDL-based design flow • VHDL design and program structure • Structural, dataflow and behavorial programs
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3 Objectives • Learn how HDL can facilitate the design process • Learn the HDL design flow • Get a high level view of the VHDL • Learn the three programming styles in VHDL
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4 What’s wrong with traditional digital design description and methodology? • Specifications? • Block diagrams? • Schematic diagrams? • Circuit descriptions and timing diagrams? • Prototyping and testing? • As a whole? – Modeling, simulations, tools, portability and reusability, test benches, verifications, …
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5 Why HDL ? HDL allows – a rigorous specification of devices independent of the underlying hardware implementation – easy reuse of hardware design modules – the development of CAD tools for design automation and documentation – a top down design methodology and testing of overall system functionality using modeling and simulation tools – verification of the design and implementation before actual fabrication or manufacturing – easy isolation of certain part of a complex design for testing and implementation
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6 HDL-based design flow – For ASICs, verification and fitting phases are usually much longer (as a fraction of overall project time).
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7 Verifying each design stage by simulation Dataflow simulator Gatelevel simulator Device simulator Simulation tools Design idea Behavioral design Behavioral simulator Data path design Logic design Physical design Manufacturing Chip or board Final testing Product sample Transistor list, layout Gate wirelist, netlist Bus and register structure Flow graph, pseudo code
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8 Top down design and bottom up implementation Design SSC1 SSC2 SS311 SSC312 SSC31 SSC3n1 SSC3n2 SSC3n SSC3 SSC41 SSC42 SSC4 SUD Implementation
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9 Verifying the first level of partitioning Behavioral model SSC1 SSC2 SSC3 SSC4 SUD Interconnection of behavioral model Compare
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10 Verifying hardware implementation of SSC1 and SSC2 Behavioral model SSC1 SSC2 SSC3 SSC4 SUD Mixed level model Compare
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11 Verifying the final design Behavioral model Compare SSC1 SSC2 SSC3 SSC41 SSC42 SSC4 SUD Mixed level model
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12 Verifying hardware implementation of SSC3 Behavioral model Compare SS311 SSC312 SSC31 SSC3n1 SSC3n2 SSC3n SSC3 Hardware level model
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Unit 4 - ERG 2020A Unit 4 Hardware Description Languages...

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