Unit 5 - ERG 2020A Unit 5 Combinational Logic II Professor...

Info iconThis preview shows pages 1–14. Sign up to view the full content.

View Full Document Right Arrow Icon
1 ERG 2020A Unit 5 Combinational Logic II Professor K.W.Cheung HSH 819 X 8348 kwcheung@ie.cuhk.edu.hk
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 Outline • Decoders • Three-state Outputs •E n c o
Background image of page 2
3 Objectives • Learn about different kinds of standard combinational circuits • Use of VHDL to describe these circuits
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
4 Decoders • General decoder structure • Typically n inputs, 2 n outputs – 2-to-4, 3-to-8, 4-to-16, etc.
Background image of page 4
5 Binary 2-to-4 decoder Note “x” (don’t care) notation.
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
6 2-to-4-decoder logic diagram
Background image of page 6
7 MSI 2-to-4 decoder • Input buffering (less load) • NAND gates (faster)
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
8 Decoder Symbol
Background image of page 8
9 VHDL structural example 2 to 4 decoder library IEEE; use IEEE.std_logic_1164.all; entity V2to4dec is port ( I0, I1, EN: in STD_LOGIC; Y0, Y1, Y2, Y3: out STD_LOGIC ); end V2to4dec; architecture V2to4dec_s of V2to4dec is signal NOTI0, NOTI1: STD_LOGIC; component inv port (I: in STD_LOGIC; O: out STD_LOGIC ); end component; component and3 port (I0, I1, I2: in STD_LOGIC; O: out STD_LOGIC ); end component; begin U1: inv port map (I0,NOTI0); U2: inv port map (I1,NOTI1); U3: and3 port map (NOTI0,NOTI1,EN,Y0); U4: and3 port map ( I0,NOTI1,EN,Y1); U5: and3 port map (NOTI0, I1,EN,Y2); U6: and3 port map ( I0, I1,EN,Y3); end V2to4dec_s;
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
10 Component declaration • Treat it like an entity. • To reuse a previously declared entity, the entity must be explicitly declared as a component inside an architecture. • Alternatively, can directly instantiate an entity inside an architecture without declaring a component. • Default directory “work” is the current working directory
Background image of page 10
11 entity inv is port (I: in STD_LOGIC; O: out STD_LOGIC ); end entity inv; architecture inv_b of inv is begin O <= not I; end architecture inv_b; entity and3 is port (I0, I1, I2: in STD_LOGIC; O: out STD_LOGIC ); end entity and3; architecture and3_b of and3 is begin O <= (I0 and I1) and I2; end architecture and3_b; architecture V2to4dec_b of V2to4dec is signal NOTI0, NOTI1: STD_LOGIC; begin U1: entity work.inv(inv_b) port map (I0, NOTI0); U2: entity work.inv(inv_b) port map (I1, NOTI1); U3: entity work.and3(and3_b) port map (NOTI0, NOTI1, EN, Y0); U4: entity work.and3(and3_b) port map ( I0, NOTI1, EN, Y1); U5: entity work.and3(and3_b) port map (NOTI0, I1, EN, Y2); U6: entity work.and3(and3_b) port map ( I0, I1, EN, Y3); end architecture V2to4dec_b;
Background image of page 11

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
12 VHDL dataflow example 2 to 4 decoder library IEEE; use IEEE.std_logic_1164.all; entity V2to4dec is port ( G: in STD_LOGIC; A: in STD_LOGIC_VECTOR (1 downto 0); Y: out STD_LOGIC_VECTOR (0 to 3) ); end V2to4dec; architecture V2to4dec_a of V2to4dec is signal Y_s: STD_LOGIC_VECTOR (0 to 3); -- internal signal begin with A select Y_s <= "1000" when "00", "0100" when "01", "0010" when "10", "0001" when "11", "0000" when others; Y <= Y_s when G='1' else "0000"; end V2to4dec_a;
Background image of page 12
13 VHDL behavioral example (1) 2 to 4 decoder architecture V2to4dec_b of V2to4dec is signal Y_s: STD_LOGIC_VECTOR (0 to 3); -- internal signal begin
Background image of page 13

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 14
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 05/18/2010 for the course INFORMATIO IEG 2810AB taught by Professor Professork.w.cheung during the Spring '09 term at CUHK.

Page1 / 65

Unit 5 - ERG 2020A Unit 5 Combinational Logic II Professor...

This preview shows document pages 1 - 14. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online