Unit 8 - ERG 2020A Unit 8 Sequential Logic II Professor...

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1 ERG 2020A Unit 8 Sequential Logic II Professor K.W.Cheung HSH 819 X 8348 kwcheung@ie.cuhk.edu.hk
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2 Outline • Registers • Counters • Shift registers •ROM
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3 Objectives • Learn about different kinds of standard sequential circuits • Use of VHDL to describe these circuits
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4 Multibit registers and latches • 74x175
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5 8-bit (octal) register • 74x374 – 3-state output
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6 Other octal registers • 74x273 – asynchronous clear • 74x377 – clock enable
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7 Octal latch • 74x373 – Output enable – Latch-enable input “C” or “G” • Register vs. latch, what’s the difference? – Register: edge-triggered behavior – Latch: output follows input when G is asserted
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8 VHDL behavioral model of a 16-bit register library IEEE; use IEEE.std_logic_1164.all; entity Vreg16 is port (CLK, CLKEN, OE_L, CLR_L: in STD_LOGIC; D: in STD_LOGIC_VECTOR(1 to 16); -- Input bus Q: out STD_LOGIC_VECTOR (1 to 16) ); -- Output bus (three-state) end Vreg16; architecture Vreg16 of Vreg16 is signal CLR, OE: STD_LOGIC; -- active-high versions of signals signal IQ: STD_LOGIC_VECTOR(1 to 16); -- internal Q signals begin process(CLK, CLR_L, CLR, OE_L, OE, IQ) begin CLR <= not CLR_L; OE <= not OE_L; if (CLR = '1') then IQ <= (others => '0'); elsif (CLK'event and CLK='1') then if (CLKEN='1') then IQ <= D; end if; end if; if OE = '1' then Q <= IQ; else Q <= (others => 'Z'); end if; end process; end Vreg16;
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9 Counters • Any sequential circuit whose state diagram is a single cycle. RESET EN EN EN EN EN EN EN EN EN EN EN EN EN
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10 LSB MSB Synchronous counter Serial enable logic
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11 LSB MSB Synchronous counter Parallel enable logic
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12 74x163 MSI 4-bit counter
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13 74x163 internal logic diagram • XOR gates embody the “T” function • Mux-like structure for loading
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14 Counter operation • Free-running ÷ 16 • Count if ENP and ENT both asserted. • Load if LD is asserted (overrides counting). • Clear if CLR is asserted (overrides loading and counting). • All operations take place on rising CLK edge. • RCO is asserted if ENT is asserted and Count = 15.
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15 Free-running 4-bit ’163 counter • “divide-by-16” counter
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16 VHDL behavioral program for a 74x163- like binary counter library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity V74x163 is port ( CLK, CLR_L, LD_L, ENP, ENT: in STD_LOGIC; D: in UNSIGNED (3 downto 0); Q: out UNSIGNED (3 downto 0); RCO: out STD_LOGIC ); end V74x163;
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This note was uploaded on 05/18/2010 for the course INFORMATIO IEG 2810AB taught by Professor Professork.w.cheung during the Spring '09 term at CUHK.

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Unit 8 - ERG 2020A Unit 8 Sequential Logic II Professor...

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