Unit 9 - ERG 2020A Unit 9 PLD CPLD FPGA Professor...

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1 ERG 2020A Unit 9 PLD, CPLD, FPGA Professor K.W.Cheung HSH 819 X 8348 [email protected]
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2 Outline • Programmable Logic Devices • Sequential PALs •C P
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3 Objectives • Learn about various kinds of standard programmable logic devices
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4 Programmable Logic Arrays (PLAs) Any combinational logic function can be realized as a sum of products. Idea: Build a large AND-OR array with lots of inputs and product terms, and programmable connections. n inputs • AND gates have 2 n inputs -- true and complement of each variable. m outputs, driven by large OR gates • Each AND gate is programmably connected to each output’s OR gate. p AND gates ( p <<2 n )
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5 Example: 4x3 PLA, 6 product terms
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6 Compact representation • Actually, closer to physical layout (“wired logic”).
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7 Some product terms
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8 PLA Electrical Design • See Section 5.3.5 -- wired-AND logic
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9 Programmable Array Logic (PALs) • How beneficial is product sharing? – Not enough to justify the extra AND array •PA L s= = > fixed
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10 • 10 primary inputs • 8 outputs, with 7 ANDs per output • 1 AND for 3-state enable • 6 outputs available as inputs – more inputs, at expense of outputs – two-pass logic, helper terms • Note inversion on outputs – output is complement of sum-of-products – newer PALs have selectable inversion
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11 Designing with PALs • Compare number of inputs and outputs of the problem with available resources in the PAL. • Write equations for each output using HDL. • Compile the HDL program, determine whether minimized equations fit in the available AND terms. • If no fit, try modifying equations or providing “helper” terms.
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12 Sequential PALs •1
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13 One output of 16R8 8 product terms to D input of flip-flop – positive edge triggered, common clock for all Q output is fed back into AND array – needed for state machines and other applications Common 3-state enable for all output pins
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14 PAL16R6 • Six registered outputs • Two combinational outputs (like the 16L8’s)
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15 GAL16V8 • Finally got it right • Each output is programmable as combinational or registered • Also has programmable output polarity
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16 GAL16V8 output logic macrocell
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17 GAL22V10 • More inputs • More product terms • More flexibility
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18 GAL22V10 output logic macrocell
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  • Spring '09
  • ProfessorK.W.Cheung
  • Input/output, Programmable logic device, Field-programmable gate array, CLB, Programmable Array Logic

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Unit 9 - ERG 2020A Unit 9 PLD CPLD FPGA Professor...

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