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Project1 - LAB 1 a1-a4 MUX b1-b4(2-to-1 output(a1-a4/b1-b4...

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LAB 1 a1-a4 output(a1-a4/b1-b4) b1-b4 sel Figure. 1 Objective : Code the behavior of a 2-to-1 MUX in VHDL. Logic : A multiplexer or a data selector is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. In figure 1, we see two input lines and one output line each of four bits wide. The selection of a particular input line is controlled by a set of control/selection lines (‘sel’). Generally, there are 2n input lines and n selection lines. Operation : Code : library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux is Port ( --First set of inputs a1,a2,a3,a4 :in std_logic;--a1 is MSB --Second set of inputs b1,b2,b3,b4 :in std_logic;--b1 is MSB --Selection line sel :in std_logic; --Output from the MUX output :out std_logic_vector(1 to 4) ); end entity mux; architecture Behavioral of mux is begin Multiplex: process(sel) begin if(sel='0') then output(4)<=a4; output(3)<=a3; output(2)<=a2; output(1)<=a1; else end if; end process Multiplex; end Behavioral; sel output ‘0’ a1-a4 ‘1’ b1-b4 MUX (2-to-1)
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LAB 2 (MSB) (LSB) a3 b3 a2 b2 a1 b1 ‘0’ carry3 carry2 carry1 output(4) output(3) output(2) output(1) Figure. 2 Objective : Code the behavior of 3 bit carry look-ahead adder in VHDL. Logic : Refer to Course Reader. The terms G i , P i , C i , and S i used in the reader has been represented here as carry_gen i , carry_prop i, carry i , and output( i ) respectively. Operation : The carry look-ahead adder depicted in figure 2 is in relation with the behavioral description given below Code : library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity adder_lookahead is Port( a1,a2,a3 :in std_logic;--a3 is MSB b1,b2,b3 :in std_logic;--b3 is MSB output :out std_logic_vector(4 downto 1) --Sum ); end entity; architecture Behavioral of adder_lookahead is signal carry_prop1,carry_prop2,carry_prop3 :std_logic; signal carry_gen1,carry_gen2,carry_gen3 :std_logic; signal carry1,carry2,carry3 :std_logic; begin process(a3,a2,a1,b3,b2,b1) begin carry_prop1<=a1 xor b1; carry_gen1<=a1 and b1; carry_prop2<=a2 xor b2; carry_gen2<=a2 and b2; carry_prop3<=a3 xor b3; carry_gen3<=a3 and b3; end process; carry_prop3 carry_gen3 carry_prop2 carry_gen2 carry_prop1 carry_gen1
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process(carry_prop1,carry_gen1) begin carry1<=carry_gen1 or (carry_prop1 and '0'); output(1)<=carry_prop1 xor '0'; end process; process(carry1) begin carry2<=carry_gen2 or (carry_prop2 and carry1); output(2)<=carry_prop2 xor carry1; end process; process(carry2) begin end process; process( ) begin end process; end Behavioral; -- hint: carry from the previous stage would form the MSB of the sum [ output(4) ]
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