Parity1 - System Synthesis - VHDL Basics F 2 - 1 System...

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System Synthesis - VHDL Basics Fö 2 - 1 Petru Eles, IDA, LiTH VHDL Basic Issues and Simulation Semantics 1. VHDL: History and Main Features 2. Basic Constructs 3. An Example: Behavioral and Structural Models 4. Concurrent Statements 5. Signals and the Wait Statement 6. The VHDL Simulation Mechanism 7. The Delay Mechanism 8. Resolved Signals 9. VHDL for System Synthesis System Synthesis - VHDL Basics Fö 2 - 2 Petru Eles, IDA, LiTH VHDL Histor y The name: VHSIC Hardware Description Language Impor tant dates: - 1983: development started with support from US government. - 1987: adopted by IEEE as a standard (IEEE Std. 1076 - 1987). - 1993: VHDL’92 adopted as a standard after re- vision of the initial version (IEEE Std. 1076 - 1993). • Work is going on for the release of new revisions (e.g. including facilities for analog modeling and simulation).
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System Synthesis - VHDL Basics Fö 2 - 3 Petru Eles, IDA, LiTH Main Features Supports the whole design process from high to low abstraction levels: - system and algorithmic level - Register Transfer (RT) level - logic level - circuit level (to some extent) Suitable for specification in - behavioral domain - structural domain System Synthesis - VHDL Basics Fö 2 - 4 Petru Eles, IDA, LiTH Main Features (cont’d) Precise simulation semantics is associated with the language definition: - specifications in VHDL can be simulated; - the simulation output is uniquely defined and in- dependent of the tool (VHDL implementation) and of the computer on which the tool runs. VHDL specifications are accepted by hardware synthesis tools. - Both the input and the output of the synthesis process are very often codified in VHDL.
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System Synthesis - VHDL Basics Fö 2 - 5 Petru Eles, IDA, LiTH Basic Constructs • The basic building block of a VHDL model is the entity. • A digital system in VHDL is modeled as an entity which itself can be composed of other entities. • An entity is described as a set of design units : - entity declaration - architecture body - package declaration - package body - configuration declaration • A design unit can be compiled separately. System Synthesis - VHDL Basics Fö 2 - 6 Petru Eles, IDA, LiTH An Example A four bit parity generator V EVEN entity PARITY is port (V: in BIT_VECTOR(3 downto 0); EVEN: out BIT); end PARITY;
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System Synthesis - VHDL Basics Fö 2 - 7 Petru Eles, IDA, LiTH An Example (cont’d) Architecture body for parity generator - behavioral architecture PARITY_BEHAVIORAL of PARITY is begin process variable NR_1: NATURAL; NR_1:=0; for I in 3 downto 0 loop if V(I)=’1’ then NR_1:=NR_1+1; end if ; end loop ; NR_1 mod 2 = 0 EVEN<=’1’ after 2.5 ns; else EVEN<=’0’ 2.5 ns; ; wait on V ; end process ; end PARITY_BEHAVIORAL; System Synthesis - VHDL Basics Fö 2 - 8 Petru Eles, IDA, LiTH An Example (cont’d) Parity generator - structural The same external interface as before; only the internal description differs.
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This note was uploaded on 05/19/2010 for the course COMPUTER E EEADS taught by Professor Drcochran during the Spring '08 term at Uni. Buckingham.

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Parity1 - System Synthesis - VHDL Basics F 2 - 1 System...

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