260030-DSD-Lab-Programs-Using-VHDL-Adders-Subtractors-Comparator-Decoder-Parity-Multiplexer-FlipFl

260030-DSD-Lab-Programs-Using-VHDL-Adders-Subtractors-Comparator-Decoder-Parity-Multiplexer-FlipFl

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Unformatted text preview: FULL ADDER AIM: To design, implement and analyze all the three models for full adder. Design: First, VHDL code for half adder was written and block was generated. Half adder block as component and basic gates, code for full adder is written. The truth tables are as follows: HALF ADDER: A B SUM CARRY 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 FULL ADDER: A B CIN SUM COUT 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 SUM = A XOR B XOR C; CARRY = AB + AC + BC; SUM 00 01 11 10 0 1 1 1 1 1 CARRY 00 01 11 10 0 1 1 1 1 1 --Structural model for Half Adder library IEEE; use IEEE.STD_LOGIC_1164.all; entity HA is port(A,B:in STD_LOGIC; Sum, Carry:out STD_LOGIC); end HA; architecture struct of HA is component myXOR port(in1,in2:in STD_LOGIC; out1:out STD_LOGIC); end component; begin X1: myXOR port map(A,B,Sum); Carry<=A and B; end struct; --Structural model for Full Adder library IEEE; use IEEE.STD_LOGIC_1164.all; entity FA is port(x,y,cin:in std_logic; s, cout:out std_logic); end FA; architecture struct of FA is signal s1,c1,c2 :std_logic; component HA port(A,B:in STD_LOGIC; sum, Carry:out STD_LOGIC); end component; begin HA1: HA port map(x,y, s1,c1); HA2: HA port map(s1,cin, s,c2); cout<=c1 or c2; end struct; hcout~0 hs~0 hs hcout hx hy RTL VIEW (Structural): Fig. Full Adder Fig. Half Adder SIMULAION WAVEFORM: The output shown above is directly taken from the SCF editor of MAX PLUSII BASE LINE. ANALYSIS: Timing Analyzer result (Structural): FLOW SUMMARY (Structural): Fitter Status : Successful - Thu Oct 19 08:44:16 2006 Quartus II Version : 6.0 Build 202 06/20/2006 SP 1 SJ Web Edition Revision Name : Adder Top-level Entity Name : FA Family : Stratix Device : EP1S10F484C5 Timing Models : Final Total logic elements : 2 / 10,570 ( < 1 % ) Total pins : 5 / 336 ( 1 % ) Total virtual pins : 0 Total memory bits : 0 / 920,448 ( 0 % ) DSP block 9-bit elements : 0 / 48 ( 0 % ) Total PLLs : 0 / 6 ( 0 % ) Total DLLs : 0 / 2 ( 0 % ) --VHDL code for DATA FLOW model of Full Adder: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity FA_DF is port(Fx, Fy, Fcin : in BIT; Fs, Fcout : out BIT); end FA_DF; architecture FA_dataflow of FA_DF is begin Fs <= Fx XOR Fy XOR Fcin; Fcout <= (Fx AND Fy) OR (Fx AND Fcin) OR (Fy AND Fcin); end FA_dataflow; FLOW SUMMARY (Data Flow): Fitter Status : Successful - Thu Oct 19 08:44:16 2006 Quartus II Version : 6.0 Build 202 06/20/2006 SP 1 SJ Web Edition Revision Name : Adder Top-level Entity Name : FA Family : Stratix Device : EP1S10F484C5 Timing Models : Final Total logic elements : 2 / 10,570 ( < 1 % ) Total pins : 5 / 336 ( 1 % ) Total virtual pins : 0 Total memory bits : 0 / 920,448 ( 0 % ) DSP block 9-bit elements : 0 / 48 ( 0 % ) Total PLLs : 0 / 6 ( 0 % ) Total DLLs : 0 / 2 ( 0 % ) SIMULATION WAVEFORM ( DATA FLOW): RTL VIEW (Data Flow):--VHDL code for BEHAVIORAL model of Full Adder library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity FA_Bhr is port(Fx, Fy, Fcin : in BIT; Fs, Fcout : out BIT); end FA_Bhr; architecture FA_struct of FA_Bhr is...
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260030-DSD-Lab-Programs-Using-VHDL-Adders-Subtractors-Comparator-Decoder-Parity-Multiplexer-FlipFl

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