lecture02

lecture02 - Introduction to Verilog design Lecture 2 ECE...

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1 Introduction to Verilog design ECE 156A 1 Lecture 2 Design flow from the book ECE 156A 2
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2 Hierarchical Design ± A chip contain many modules ± A module may contain other Chi modules – no recursion ± A module uses predefined cells ± Everything is based on primitives Chip Modules Cells ECE 156A 3 Primitives Hierarchical design flow Multi-Core system SW/HW co-design, multiple cores (SW/HW system verification) Functional units Full chip Arithmetic blocks common bus structures ALU, Float Point Unit, Filter, Memory Management, Scheduler, etc. (RTL verification can be hard) Processor, DSP, MPEG, etc. (Functionality is specified in books) ECE 156A 4 Cell Library Block designs Certify that layouts can be manufactured with high yield (This may be Fab dependent) Arithmetic blocks, common bus structures, Cross-bar switches, decoders, etc. (May be custom designed)
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3 Advantages ± When working at a particular level of design, we don’t need to worry about all detail below – When putting an 8-bit adder, you don’t need to worry about how 1-bit adder is done – Optimization can be done independently at each level ± Since no detail is involved, it is easier to replace the designs with other implementations You can easily change the 1 bit adder to another ECE 156A 5 – You can easily change the 1-bit adder to another implementation without changing the 8-bit verilog module – You can change the technology from 0.13 micron to 0.1 micron without changing the verilog RTL Primtives and design model ± Verilog includes 26 predefined models of logic gates called primitives ± Primitives are the most basic functional components that can be used to build mode ) a design that can be used to build ( model – Their functions are built into the language by internal truth table ± The output port of a primitive is the first in the list ECE 156A 6
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4 Verilog primitives for combinational logic n-input n-output, 3-state and buf nand not or bufif0 nor bufif1 xor notif0 xnor notif1 ECE 156A 7 ± n-input: Any number of inputs and 1 output ± n-output: Any number of outputs and 1 input List of Verilog primitives ± Gates – and, nand, or, nor, xor, xnor, buf, not ± Tri-State – bufif0, bufif1, notif0, notif1 ± MOS – nmos, pmos, rnmos, rpmos ± CMOS – cmos, rcmos ± Bi-directional tran tranif0 tranif1 rtran rtranif0 rtranif1 ECE 156A 8 – tran, tranif0, tranif1, rtran, rtranif0, rtranif1 ± Pull – pullup, pulldown
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5 Structural Verilog model ECE 156A 9 Verilog Behavior of D FF module Flip_flop (q, data_in, clk, rst); input data in, clk, rst; _ output q; reg q; always @ ( posedge clk) begin i (rst == 1) q = 0 Declaration of Synchronous Behavior rst data_in clk q Block Di ECE 156A 10 if (rst == 1) q = 0; else q = data_in; end endmodule Procedural Statements Diagram
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6 Block diagram view Add_half a b sum c ou Block Diagram c_out Block Diagram sum a b c_out_bar One Implementation ECE 156A 11 c_out
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lecture02 - Introduction to Verilog design Lecture 2 ECE...

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